SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35059 | 1 | T9 | 321 | T36 | 379 | T37 | 394 | ||||
others[1] | 34955 | 1 | T9 | 268 | T36 | 390 | T37 | 350 | ||||
others[2] | 35097 | 1 | T9 | 320 | T36 | 395 | T37 | 399 | ||||
others[3] | 58354 | 1 | T9 | 501 | T36 | 682 | T37 | 714 | ||||
false | 18680 | 1 | T6 | 206 | T9 | 50 | T24 | 44 | ||||
true | 28466 | 1 | T1 | 13 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35161 | 1 | T9 | 290 | T36 | 405 | T37 | 418 | ||||
others[1] | 34928 | 1 | T9 | 294 | T36 | 429 | T37 | 402 | ||||
others[2] | 34743 | 1 | T9 | 292 | T36 | 382 | T37 | 376 | ||||
others[3] | 58680 | 1 | T9 | 524 | T36 | 658 | T37 | 690 | ||||
false | 11933 | 1 | T6 | 103 | T9 | 50 | T24 | 22 | ||||
true | 21784 | 1 | T1 | 13 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 645 | 1 | T6 | 4 | T8 | 2 | T24 | 3 | ||||
others[1] | 671 | 1 | T5 | 1 | T6 | 6 | T8 | 1 | ||||
others[2] | 656 | 1 | T5 | 1 | T6 | 2 | T24 | 2 | ||||
others[3] | 1112 | 1 | T1 | 3 | T5 | 3 | T6 | 4 | ||||
false | 13160 | 1 | T1 | 19 | T2 | 1 | T3 | 1 | ||||
true | 3912 | 1 | T1 | 3 | T5 | 4 | T6 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |