Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24735441	14837	0	0
intr_enable_rd_A	24735441	42985	0	0
reset_en_rd_A	24735441	1688	0	0
reset_en_regwen_rd_A	24735441	1377	0	0
wake_info_capture_dis_rd_A	24735441	1482	0	0
wakeup_en_rd_A	24735441	1932	0	0
wakeup_en_regwen_rd_A	24735441	1408	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	14837	0	0
T6	186170	54	0	0
T7	1520	0	0	0
T8	4023	0	0	0
T9	19268	0	0	0
T10	3008	0	0	0
T20	0	42	0	0
T21	0	12	0	0
T24	16972	0	0	0
T57	10548	0	0	0
T65	0	3	0	0
T71	1652	0	0	0
T72	1186	0	0	0
T74	5047	0	0	0
T75	0	15	0	0
T76	0	5	0	0
T135	0	8	0	0
T136	0	18	0	0
T137	0	107	0	0
T138	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	42985	0	0
T9	19268	147	0	0
T10	3008	0	0	0
T19	3347	0	0	0
T22	0	194	0	0
T23	0	22	0	0
T24	16972	142	0	0
T51	8632	0	0	0
T57	10548	0	0	0
T71	1652	0	0	0
T72	1186	0	0	0
T73	0	167	0	0
T74	5047	74	0	0
T139	4402	92	0	0
T140	0	29	0	0
T141	0	126	0	0
T142	0	34	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	1688	0	0
T48	0	24	0	0
T80	0	7	0	0
T107	1054	0	0	0
T136	406705	1	0	0
T143	0	1	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	17	0	0
T147	0	5	0	0
T148	0	4	0	0
T149	0	5	0	0
T150	5516	0	0	0
T151	1720	0	0	0
T152	35523	0	0	0
T153	7585	0	0	0
T154	2393	0	0	0
T155	30413	0	0	0
T156	29315	0	0	0
T157	3656	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	1377	0	0
T14	794	0	0	0
T45	0	22	0	0
T48	0	15	0	0
T65	54591	7	0	0
T80	0	20	0	0
T104	53108	0	0	0
T136	0	3	0	0
T143	0	5	0	0
T144	0	2	0	0
T145	0	8	0	0
T147	0	12	0	0
T149	0	3	0	0
T158	1156	0	0	0
T159	3604	0	0	0
T160	3305	0	0	0
T161	15211	0	0	0
T162	2920	0	0	0
T163	1366	0	0	0
T164	3013	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	1482	0	0
T14	794	0	0	0
T48	0	10	0	0
T65	54591	7	0	0
T80	0	20	0	0
T104	53108	0	0	0
T136	0	7	0	0
T143	0	9	0	0
T144	0	8	0	0
T145	0	8	0	0
T146	0	12	0	0
T147	0	9	0	0
T148	0	1	0	0
T158	1156	0	0	0
T159	3604	0	0	0
T160	3305	0	0	0
T161	15211	0	0	0
T162	2920	0	0	0
T163	1366	0	0	0
T164	3013	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	1932	0	0
T48	0	15	0	0
T50	0	8	0	0
T80	0	27	0	0
T107	1054	0	0	0
T136	406705	2	0	0
T143	0	10	0	0
T145	0	2	0	0
T146	0	9	0	0
T147	0	26	0	0
T149	0	4	0	0
T150	5516	0	0	0
T151	1720	0	0	0
T152	35523	0	0	0
T153	7585	0	0	0
T154	2393	0	0	0
T155	30413	0	0	0
T156	29315	0	0	0
T157	3656	0	0	0
T165	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24735441	1408	0	0
T48	0	18	0	0
T50	0	6	0	0
T80	0	20	0	0
T107	1054	0	0	0
T136	406705	7	0	0
T143	0	7	0	0
T144	0	4	0	0
T145	0	12	0	0
T146	0	9	0	0
T147	0	7	0	0
T149	0	7	0	0
T150	5516	0	0	0
T151	1720	0	0	0
T152	35523	0	0	0
T153	7585	0	0	0
T154	2393	0	0	0
T155	30413	0	0	0
T156	29315	0	0	0
T157	3656	0	0	0