SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 100.00 | 83.87 | 99.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 100.00 | 83.87 | 99.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1910 | 1910 | 0 | 0 |
OutputsKnown_A | 48252652 | 47237186 | 0 | 0 |
gen_flops.OutputDelay_A | 48252652 | 47196416 | 0 | 5730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1910 | 1910 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48252652 | 47237186 | 0 | 0 |
T1 | 164672 | 162664 | 0 | 0 |
T2 | 6756 | 6580 | 0 | 0 |
T3 | 31348 | 31188 | 0 | 0 |
T4 | 2706 | 2526 | 0 | 0 |
T5 | 10264 | 8508 | 0 | 0 |
T6 | 372340 | 363130 | 0 | 0 |
T7 | 3040 | 2362 | 0 | 0 |
T8 | 8046 | 6088 | 0 | 0 |
T9 | 38536 | 38314 | 0 | 0 |
T10 | 6016 | 5724 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48252652 | 47196416 | 0 | 5730 |
T1 | 164672 | 162586 | 0 | 6 |
T2 | 6756 | 6574 | 0 | 6 |
T3 | 31348 | 31182 | 0 | 6 |
T4 | 2706 | 2520 | 0 | 6 |
T5 | 10264 | 8436 | 0 | 6 |
T6 | 372340 | 362740 | 0 | 6 |
T7 | 3040 | 2332 | 0 | 6 |
T8 | 8046 | 6010 | 0 | 6 |
T9 | 38536 | 38302 | 0 | 6 |
T10 | 6016 | 5712 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 955 | 955 | 0 | 0 |
OutputsKnown_A | 24126326 | 23618593 | 0 | 0 |
gen_flops.OutputDelay_A | 24126326 | 23598208 | 0 | 2865 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 955 | 955 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24126326 | 23618593 | 0 | 0 |
T1 | 82336 | 81332 | 0 | 0 |
T2 | 3378 | 3290 | 0 | 0 |
T3 | 15674 | 15594 | 0 | 0 |
T4 | 1353 | 1263 | 0 | 0 |
T5 | 5132 | 4254 | 0 | 0 |
T6 | 186170 | 181565 | 0 | 0 |
T7 | 1520 | 1181 | 0 | 0 |
T8 | 4023 | 3044 | 0 | 0 |
T9 | 19268 | 19157 | 0 | 0 |
T10 | 3008 | 2862 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24126326 | 23598208 | 0 | 2865 |
T1 | 82336 | 81293 | 0 | 3 |
T2 | 3378 | 3287 | 0 | 3 |
T3 | 15674 | 15591 | 0 | 3 |
T4 | 1353 | 1260 | 0 | 3 |
T5 | 5132 | 4218 | 0 | 3 |
T6 | 186170 | 181370 | 0 | 3 |
T7 | 1520 | 1166 | 0 | 3 |
T8 | 4023 | 3005 | 0 | 3 |
T9 | 19268 | 19151 | 0 | 3 |
T10 | 3008 | 2856 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 955 | 955 | 0 | 0 |
OutputsKnown_A | 24126326 | 23618593 | 0 | 0 |
gen_flops.OutputDelay_A | 24126326 | 23598208 | 0 | 2865 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 955 | 955 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24126326 | 23618593 | 0 | 0 |
T1 | 82336 | 81332 | 0 | 0 |
T2 | 3378 | 3290 | 0 | 0 |
T3 | 15674 | 15594 | 0 | 0 |
T4 | 1353 | 1263 | 0 | 0 |
T5 | 5132 | 4254 | 0 | 0 |
T6 | 186170 | 181565 | 0 | 0 |
T7 | 1520 | 1181 | 0 | 0 |
T8 | 4023 | 3044 | 0 | 0 |
T9 | 19268 | 19157 | 0 | 0 |
T10 | 3008 | 2862 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24126326 | 23598208 | 0 | 2865 |
T1 | 82336 | 81293 | 0 | 3 |
T2 | 3378 | 3287 | 0 | 3 |
T3 | 15674 | 15591 | 0 | 3 |
T4 | 1353 | 1260 | 0 | 3 |
T5 | 5132 | 4218 | 0 | 3 |
T6 | 186170 | 181370 | 0 | 3 |
T7 | 1520 | 1166 | 0 | 3 |
T8 | 4023 | 3005 | 0 | 3 |
T9 | 19268 | 19151 | 0 | 3 |
T10 | 3008 | 2856 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |