Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72378978	138937	0	0
StatusRise_A	72378978	155085	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72378978	138937	0	0
T1	247008	340	0	0
T2	10134	37	0	0
T3	47022	3	0	0
T4	4059	8	0	0
T5	15396	54	0	0
T6	558510	1523	0	0
T7	4560	12	0	0
T8	12069	54	0	0
T9	57804	220	0	0
T10	9024	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72378978	155085	0	0
T1	247008	374	0	0
T2	10134	39	0	0
T3	47022	6	0	0
T4	4059	11	0	0
T5	15396	57	0	0
T6	558510	1695	0	0
T7	4560	15	0	0
T8	12069	60	0	0
T9	57804	225	0	0
T10	9024	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24126326	51634	0	0
StatusRise_A	24126326	57476	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	51634	0	0
T1	82336	123	0	0
T2	3378	16	0	0
T3	15674	1	0	0
T4	1353	3	0	0
T5	5132	18	0	0
T6	186170	566	0	0
T7	1520	4	0	0
T8	4023	18	0	0
T9	19268	90	0	0
T10	3008	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	57476	0	0
T1	82336	136	0	0
T2	3378	17	0	0
T3	15674	2	0	0
T4	1353	4	0	0
T5	5132	19	0	0
T6	186170	630	0	0
T7	1520	5	0	0
T8	4023	20	0	0
T9	19268	92	0	0
T10	3008	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24126326	51634	0	0
StatusRise_A	24126326	57476	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	51634	0	0
T1	82336	123	0	0
T2	3378	16	0	0
T3	15674	1	0	0
T4	1353	3	0	0
T5	5132	18	0	0
T6	186170	566	0	0
T7	1520	4	0	0
T8	4023	18	0	0
T9	19268	90	0	0
T10	3008	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	57476	0	0
T1	82336	136	0	0
T2	3378	17	0	0
T3	15674	2	0	0
T4	1353	4	0	0
T5	5132	19	0	0
T6	186170	630	0	0
T7	1520	5	0	0
T8	4023	20	0	0
T9	19268	92	0	0
T10	3008	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24126326	35669	0	0
StatusRise_A	24126326	40133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	35669	0	0
T1	82336	94	0	0
T2	3378	5	0	0
T3	15674	1	0	0
T4	1353	2	0	0
T5	5132	18	0	0
T6	186170	391	0	0
T7	1520	4	0	0
T8	4023	18	0	0
T9	19268	40	0	0
T10	3008	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	40133	0	0
T1	82336	102	0	0
T2	3378	5	0	0
T3	15674	2	0	0
T4	1353	3	0	0
T5	5132	19	0	0
T6	186170	435	0	0
T7	1520	5	0	0
T8	4023	20	0	0
T9	19268	41	0	0
T10	3008	6	0	0