Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24126922	5124	0	0
EscTimeoutStoppedByClReset_A	24126326	3490477	0	0
EscTimeoutTriggersReset_A	4740920	296	0	0
RomAllowActiveState_A	24126326	57061	0	0
RomAllowCheckGoodState_A	24126326	57111	0	0
RomBlockActiveState_A	24126326	23995	0	0
RomBlockCheckGoodState_A	24126326	441394	0	0
RomIntgChkDisFalse_A	24126326	23465278	0	0
RomIntgChkDisTrue_A	24126326	153315	0	0
RstreqChkEsctimeout_A	24126326	4202	0	0
RstreqChkFsmterm_A	24126326	180	0	0
RstreqChkGlbesc_A	24126326	4202	0	0
RstreqChkMainpd_A	24126326	1025395	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126922	5124	0	0
T3	15674	156	0	0
T4	1353	0	0	0
T5	5133	0	0	0
T6	186170	0	0	0
T7	1521	0	0	0
T8	4023	0	0	0
T9	19268	0	0	0
T10	3009	0	0	0
T12	0	19	0	0
T40	0	55	0	0
T57	10548	0	0	0
T71	1653	0	0	0
T161	0	32	0	0
T166	0	73	0	0
T167	0	243	0	0
T168	0	13	0	0
T169	0	57	0	0
T170	0	182	0	0
T171	0	30	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	3490477	0	0
T1	82336	15894	0	0
T2	3378	381	0	0
T3	15674	27	0	0
T4	1353	0	0	0
T5	5132	453	0	0
T6	186170	28240	0	0
T7	1520	66	0	0
T8	4023	390	0	0
T9	19268	2130	0	0
T10	3008	8	0	0
T71	0	27	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4740920	296	0	0
T3	200	2	0	0
T4	207	0	0	0
T5	677	0	0	0
T6	35686	0	0	0
T7	502	0	0	0
T8	817	0	0	0
T9	13057	0	0	0
T10	240	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T40	0	3	0	0
T57	1115	0	0	0
T71	500	0	0	0
T161	0	2	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	57061	0	0
T1	82336	136	0	0
T2	3378	17	0	0
T3	15674	2	0	0
T4	1353	4	0	0
T5	5132	12	0	0
T6	186170	629	0	0
T7	1520	5	0	0
T8	4023	13	0	0
T9	19268	92	0	0
T10	3008	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	57111	0	0
T1	82336	136	0	0
T2	3378	17	0	0
T3	15674	2	0	0
T4	1353	4	0	0
T5	5132	13	0	0
T6	186170	629	0	0
T7	1520	5	0	0
T8	4023	14	0	0
T9	19268	92	0	0
T10	3008	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	23995	0	0
T22	23474	5	0	0
T23	5395	1191	0	0
T41	2274	0	0	0
T42	4851	1471	0	0
T73	33532	0	0	0
T140	18517	0	0	0
T163	0	141	0	0
T172	0	804	0	0
T173	0	1189	0	0
T174	0	671	0	0
T175	0	295	0	0
T176	0	266	0	0
T177	0	206	0	0
T178	6030	0	0	0
T179	1261	0	0	0
T180	2708	0	0	0
T181	2398	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	441394	0	0
T6	186170	2362	0	0
T7	1520	0	0	0
T8	4023	0	0	0
T9	19268	842	0	0
T10	3008	0	0	0
T22	0	1180	0	0
T23	0	1049	0	0
T24	16972	504	0	0
T36	0	2240	0	0
T37	0	4018	0	0
T42	0	878	0	0
T57	10548	0	0	0
T71	1652	0	0	0
T72	1186	0	0	0
T74	5047	0	0	0
T140	0	341	0	0
T178	0	207	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	23465278	0	0
T1	82336	81332	0	0
T2	3378	3290	0	0
T3	15674	15594	0	0
T4	1353	1263	0	0
T5	5132	4254	0	0
T6	186170	181565	0	0
T7	1520	1181	0	0
T8	4023	3044	0	0
T9	19268	18861	0	0
T10	3008	2862	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	153315	0	0
T9	19268	296	0	0
T10	3008	0	0	0
T19	3347	0	0	0
T22	0	233	0	0
T23	0	297	0	0
T24	16972	0	0	0
T42	0	1198	0	0
T51	8632	0	0	0
T57	10548	0	0	0
T71	1652	0	0	0
T72	1186	0	0	0
T74	5047	0	0	0
T139	4402	0	0	0
T163	0	127	0	0
T172	0	479	0	0
T174	0	199	0	0
T175	0	35	0	0
T182	0	11416	0	0
T183	0	1743	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	4202	0	0
T1	82336	4	0	0
T2	3378	0	0	0
T3	15674	1	0	0
T4	1353	0	0	0
T5	5132	5	0	0
T6	186170	26	0	0
T7	1520	0	0	0
T8	4023	3	0	0
T9	19268	0	0	0
T10	3008	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	0	10	0	0
T38	0	5	0	0
T40	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	180	0	0
T16	38814	40	0	0
T17	0	40	0	0
T18	0	20	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	2212	0	0	0
T28	2219	0	0	0
T29	13078	0	0	0
T30	3706	0	0	0
T31	6274	0	0	0
T32	3600	0	0	0
T33	55133	0	0	0
T34	6001	0	0	0
T35	1284	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	4202	0	0
T1	82336	4	0	0
T2	3378	0	0	0
T3	15674	1	0	0
T4	1353	0	0	0
T5	5132	5	0	0
T6	186170	26	0	0
T7	1520	0	0	0
T8	4023	3	0	0
T9	19268	0	0	0
T10	3008	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	0	10	0	0
T38	0	5	0	0
T40	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24126326	1025395	0	0
T1	82336	495	0	0
T2	3378	0	0	0
T3	15674	0	0	0
T4	1353	0	0	0
T5	5132	234	0	0
T6	186170	5054	0	0
T7	1520	0	0	0
T8	4023	131	0	0
T9	19268	1384	0	0
T10	3008	0	0	0
T13	0	22	0	0
T24	0	968	0	0
T36	0	3808	0	0
T37	0	6115	0	0
T38	0	613	0	0