Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	500281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185886

1

T1

47

T2

1

T3

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	354230	1			T1	116		T2	1		T3	394
values[0x0]	165942	1			T1	61		T3	178		T7	69
values[0x1]	165995	1			T1	55		T3	211		T7	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	395893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

290274

1

T1

81

T2

1

T3

291

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2117	1			T3	4		T7	6		T16	4
valid_sources[0x01]	5075	1			T3	2		T16	6		T40	3
valid_sources[0x02]	2938	1			T3	3		T16	9		T40	2
valid_sources[0x03]	2181	1			T3	2		T11	1		T12	1
valid_sources[0x04]	2146	1			T3	7		T7	2		T11	1
valid_sources[0x05]	2063	1			T7	7		T11	3		T16	6
valid_sources[0x06]	2297	1			T3	6		T11	2		T16	4
valid_sources[0x07]	3059	1			T3	4		T11	1		T16	8
valid_sources[0x08]	2149	1			T3	4		T11	1		T16	6
valid_sources[0x09]	2162	1			T3	3		T7	2		T46	1
valid_sources[0x0a]	2005	1			T3	3		T11	3		T16	10
valid_sources[0x0b]	1999	1			T3	1		T7	3		T16	9
valid_sources[0x0c]	2045	1			T3	4		T11	1		T16	7
valid_sources[0x0d]	2416	1			T3	2		T7	3		T11	2
valid_sources[0x0e]	4372	1			T3	4		T16	7		T40	2
valid_sources[0x0f]	3637	1			T3	5		T7	1		T11	1
valid_sources[0x10]	2108	1			T3	4		T11	2		T16	10
valid_sources[0x11]	2252	1			T3	3		T7	1		T11	1
valid_sources[0x12]	3253	1			T3	3		T11	1		T16	6
valid_sources[0x13]	2127	1			T3	4		T16	6		T40	2
valid_sources[0x14]	2557	1			T3	6		T7	2		T11	2
valid_sources[0x15]	2500	1			T3	2		T7	3		T16	8
valid_sources[0x16]	2641	1			T3	4		T7	7		T16	6
valid_sources[0x17]	2320	1			T3	1		T16	4		T20	56
valid_sources[0x18]	2098	1			T3	6		T7	8		T16	6
valid_sources[0x19]	2109	1			T3	1		T7	4		T11	2
valid_sources[0x1a]	2245	1			T3	2		T7	15		T16	3
valid_sources[0x1b]	2353	1			T3	1		T16	2		T46	1
valid_sources[0x1c]	2018	1			T3	5		T7	1		T11	1
valid_sources[0x1d]	4340	1			T3	1		T11	2		T16	16
valid_sources[0x1e]	2284	1			T3	4		T11	1		T16	14
valid_sources[0x1f]	2365	1			T3	6		T7	13		T11	3
valid_sources[0x20]	2975	1			T12	1		T16	5		T40	3
valid_sources[0x21]	2756	1			T3	4		T11	2		T16	8
valid_sources[0x22]	2034	1			T3	1		T11	2		T16	2
valid_sources[0x23]	4711	1			T11	4		T16	9		T47	1
valid_sources[0x24]	2167	1			T3	4		T11	1		T16	6
valid_sources[0x25]	4814	1			T11	1		T16	7		T40	1
valid_sources[0x26]	2114	1			T3	5		T7	6		T11	5
valid_sources[0x27]	2070	1			T3	3		T16	8		T46	1
valid_sources[0x28]	2274	1			T3	2		T16	13		T40	4
valid_sources[0x29]	2623	1			T3	1		T7	2		T11	2
valid_sources[0x2a]	2108	1			T3	5		T11	1		T16	4
valid_sources[0x2b]	2152	1			T3	5		T7	1		T16	8
valid_sources[0x2c]	2520	1			T3	2		T12	1		T16	9
valid_sources[0x2d]	2533	1			T3	3		T7	4		T11	1
valid_sources[0x2e]	3904	1			T3	2		T11	1		T16	5
valid_sources[0x2f]	2390	1			T3	1		T7	2		T11	4
valid_sources[0x30]	3158	1			T3	4		T7	3		T16	6
valid_sources[0x31]	2235	1			T3	2		T7	4		T11	1
valid_sources[0x32]	2366	1			T3	1		T11	1		T16	4
valid_sources[0x33]	4691	1			T3	2		T16	5		T40	2
valid_sources[0x34]	2224	1			T3	4		T7	2		T16	1
valid_sources[0x35]	2035	1			T3	6		T11	1		T16	1
valid_sources[0x36]	2227	1			T3	4		T11	3		T16	11
valid_sources[0x37]	2194	1			T3	4		T16	5		T40	5
valid_sources[0x38]	2037	1			T3	4		T11	1		T16	4
valid_sources[0x39]	2046	1			T3	3		T16	9		T42	2
valid_sources[0x3a]	4120	1			T3	5		T7	4		T11	1
valid_sources[0x3b]	2246	1			T3	7		T7	1		T42	1
valid_sources[0x3c]	2216	1			T3	4		T7	2		T16	13
valid_sources[0x3d]	2154	1			T3	6		T16	5		T40	3
valid_sources[0x3e]	3929	1			T3	3		T7	2		T11	1
valid_sources[0x3f]	2487	1			T3	1		T11	3		T16	3
valid_sources[0x40]	2555	1			T3	1		T7	3		T11	3
valid_sources[0x41]	3965	1			T3	3		T7	4		T11	1
valid_sources[0x42]	2266	1			T3	4		T11	1		T16	7
valid_sources[0x43]	2298	1			T3	2		T11	2		T16	3
valid_sources[0x44]	3110	1			T3	2		T7	1		T16	5
valid_sources[0x45]	4517	1			T3	3		T11	3		T16	3
valid_sources[0x46]	2446	1			T3	2		T16	3		T46	1
valid_sources[0x47]	2080	1			T3	3		T11	1		T16	7
valid_sources[0x48]	2706	1			T3	4		T40	2		T20	51
valid_sources[0x49]	2046	1			T3	3		T11	3		T16	6
valid_sources[0x4a]	2381	1			T3	3		T7	1		T16	12
valid_sources[0x4b]	2253	1			T3	2		T11	1		T16	5
valid_sources[0x4c]	2183	1			T3	5		T12	1		T16	14
valid_sources[0x4d]	2453	1			T3	6		T7	4		T16	11
valid_sources[0x4e]	2095	1			T3	2		T12	2		T16	5
valid_sources[0x4f]	2212	1			T3	2		T7	1		T11	1
valid_sources[0x50]	2485	1			T3	6		T16	2		T81	1
valid_sources[0x51]	3064	1			T3	2		T16	4		T40	2
valid_sources[0x52]	2117	1			T3	1		T7	4		T16	8
valid_sources[0x53]	5214	1			T3	7		T16	7		T40	3
valid_sources[0x54]	2066	1			T3	2		T11	1		T16	5
valid_sources[0x55]	2289	1			T3	1		T7	8		T11	1
valid_sources[0x56]	2085	1			T11	1		T16	2		T177	1
valid_sources[0x57]	2190	1			T3	2		T16	4		T40	1
valid_sources[0x58]	2153	1			T3	3		T7	4		T16	9
valid_sources[0x59]	2059	1			T3	6		T7	4		T11	1
valid_sources[0x5a]	2462	1			T3	4		T16	12		T40	4
valid_sources[0x5b]	2089	1			T3	1		T16	6		T46	1
valid_sources[0x5c]	2482	1			T3	1		T12	2		T16	3
valid_sources[0x5d]	2031	1			T3	4		T16	14		T42	2
valid_sources[0x5e]	2651	1			T3	2		T7	26		T16	8
valid_sources[0x5f]	2665	1			T3	3		T7	2		T16	16
valid_sources[0x60]	2050	1			T3	2		T7	5		T11	1
valid_sources[0x61]	2201	1			T7	1		T11	1		T16	7
valid_sources[0x62]	2015	1			T3	4		T11	2		T12	1
valid_sources[0x63]	3489	1			T3	4		T11	2		T16	9
valid_sources[0x64]	4103	1			T3	2		T7	2		T16	4
valid_sources[0x65]	2174	1			T3	3		T11	1		T16	1
valid_sources[0x66]	2505	1			T3	5		T7	5		T11	1
valid_sources[0x67]	2148	1			T3	4		T7	1		T11	1
valid_sources[0x68]	5037	1			T3	5		T16	4		T40	1
valid_sources[0x69]	2478	1			T3	2		T11	2		T16	6
valid_sources[0x6a]	2199	1			T3	1		T7	1		T12	1
valid_sources[0x6b]	2132	1			T3	1		T7	3		T16	5
valid_sources[0x6c]	1982	1			T3	2		T11	2		T16	2
valid_sources[0x6d]	2024	1			T3	5		T16	14		T40	2
valid_sources[0x6e]	2090	1			T3	2		T7	4		T16	5
valid_sources[0x6f]	3492	1			T3	4		T7	3		T11	2
valid_sources[0x70]	1990	1			T3	1		T11	2		T16	9
valid_sources[0x71]	2381	1			T3	7		T11	1		T16	6
valid_sources[0x72]	3288	1			T3	3		T7	1		T16	7
valid_sources[0x73]	2152	1			T16	2		T40	2		T20	52
valid_sources[0x74]	2402	1			T3	5		T7	5		T12	1
valid_sources[0x75]	2391	1			T3	1		T11	4		T16	3
valid_sources[0x76]	2145	1			T3	2		T7	5		T12	2
valid_sources[0x77]	2907	1			T3	3		T7	6		T11	2
valid_sources[0x78]	2348	1			T3	2		T7	1		T11	1
valid_sources[0x79]	2295	1			T3	3		T11	1		T16	5
valid_sources[0x7a]	2807	1			T3	3		T11	1		T16	7
valid_sources[0x7b]	2408	1			T7	5		T11	1		T12	2
valid_sources[0x7c]	2275	1			T3	4		T16	5		T46	1
valid_sources[0x7d]	2352	1			T3	3		T7	1		T16	4
valid_sources[0x7e]	2384	1			T3	4		T7	7		T11	1
valid_sources[0x7f]	2642	1			T3	3		T16	5		T81	4
valid_sources[0x80]	3910	1			T16	8		T40	1		T20	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91044

1

T1

17

T2

1

T3

82

values[0x0]

all_enables

biggest_size

61589

1

T1

22

T3

51

T7

24

values[0x1]

all_enables

biggest_size

33253

1

T1

8

T3

42

T7

10