SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34810 | 1 | T51 | 406 | T24 | 313 | T193 | 288 | ||||
others[1] | 34521 | 1 | T51 | 400 | T24 | 279 | T193 | 295 | ||||
others[2] | 34809 | 1 | T51 | 367 | T23 | 1 | T24 | 305 | ||||
others[3] | 57849 | 1 | T51 | 703 | T24 | 501 | T25 | 1 | ||||
false | 17870 | 1 | T3 | 26 | T12 | 2 | T16 | 44 | ||||
true | 27753 | 1 | T1 | 1 | T2 | 2 | T3 | 38 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34718 | 1 | T51 | 391 | T24 | 322 | T193 | 265 | ||||
others[1] | 34834 | 1 | T51 | 405 | T23 | 1 | T24 | 303 | ||||
others[2] | 34606 | 1 | T51 | 424 | T24 | 302 | T193 | 306 | ||||
others[3] | 57887 | 1 | T51 | 648 | T24 | 490 | T25 | 1 | ||||
false | 11507 | 1 | T3 | 13 | T12 | 1 | T16 | 22 | ||||
true | 21448 | 1 | T1 | 1 | T2 | 2 | T3 | 25 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 712 | 1 | T3 | 2 | T11 | 6 | T13 | 1 | ||||
others[1] | 690 | 1 | T11 | 3 | T16 | 3 | T37 | 2 | ||||
others[2] | 733 | 1 | T3 | 1 | T11 | 7 | T16 | 2 | ||||
others[3] | 1167 | 1 | T3 | 1 | T11 | 11 | T13 | 2 | ||||
false | 13700 | 1 | T1 | 1 | T2 | 2 | T3 | 21 | ||||
true | 4157 | 1 | T3 | 5 | T11 | 1 | T13 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |