Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T16,T46

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21905742	5847	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21905742	219414	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21905742	8953584	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21905742	219410	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21905742	5847	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21905742	219414	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21905742	8953584	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21905742	219410	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	5847	0	0
T3	25576	7	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	2	0	0
T13	3068	0	0	0
T16	29126	14	0	0
T20	0	84	0	0
T37	2663	0	0	0
T38	0	5	0	0
T39	0	9	0	0
T41	0	16	0	0
T46	0	3	0	0
T47	0	3	0	0
T81	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	219414	0	0
T3	25576	185	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	147	0	0
T13	3068	0	0	0
T16	29126	412	0	0
T20	0	1696	0	0
T37	2663	0	0	0
T38	0	271	0	0
T39	0	214	0	0
T41	0	1266	0	0
T46	0	363	0	0
T47	0	504	0	0
T81	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	8953584	0	0
T1	10108	6027	0	0
T2	1319	0	0	0
T3	25576	9787	0	0
T7	2936	1535	0	0
T8	10021	7239	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	1120	0	0
T13	3068	0	0	0
T16	0	11502	0	0
T46	0	992	0	0
T61	0	401	0	0
T81	0	1420	0	0
T82	0	4035	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	219410	0	0
T3	25576	185	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	147	0	0
T13	3068	0	0	0
T16	29126	412	0	0
T20	0	1696	0	0
T37	2663	0	0	0
T38	0	271	0	0
T39	0	214	0	0
T41	0	1266	0	0
T46	0	363	0	0
T47	0	504	0	0
T81	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	5847	0	0
T3	25576	7	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	2	0	0
T13	3068	0	0	0
T16	29126	14	0	0
T20	0	84	0	0
T37	2663	0	0	0
T38	0	5	0	0
T39	0	9	0	0
T41	0	16	0	0
T46	0	3	0	0
T47	0	3	0	0
T81	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	219414	0	0
T3	25576	185	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	147	0	0
T13	3068	0	0	0
T16	29126	412	0	0
T20	0	1696	0	0
T37	2663	0	0	0
T38	0	271	0	0
T39	0	214	0	0
T41	0	1266	0	0
T46	0	363	0	0
T47	0	504	0	0
T81	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	8953584	0	0
T1	10108	6027	0	0
T2	1319	0	0	0
T3	25576	9787	0	0
T7	2936	1535	0	0
T8	10021	7239	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	1120	0	0
T13	3068	0	0	0
T16	0	11502	0	0
T46	0	992	0	0
T61	0	401	0	0
T81	0	1420	0	0
T82	0	4035	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	219410	0	0
T3	25576	185	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	147	0	0
T13	3068	0	0	0
T16	29126	412	0	0
T20	0	1696	0	0
T37	2663	0	0	0
T38	0	271	0	0
T39	0	214	0	0
T41	0	1266	0	0
T46	0	363	0	0
T47	0	504	0	0
T81	0	13	0	0