Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22503737	13517	0	0
intr_enable_rd_A	22503737	41006	0	0
reset_en_rd_A	22503737	1180	0	0
reset_en_regwen_rd_A	22503737	987	0	0
wake_info_capture_dis_rd_A	22503737	1039	0	0
wakeup_en_rd_A	22503737	1664	0	0
wakeup_en_regwen_rd_A	22503737	1023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	13517	0	0
T20	388050	6	0	0
T21	0	14	0	0
T22	0	100	0	0
T41	95280	0	0	0
T48	4611	0	0	0
T49	7782	0	0	0
T50	1686	0	0	0
T55	0	4	0	0
T74	0	13	0	0
T85	0	72	0	0
T132	0	4	0	0
T133	0	17	0	0
T134	0	11	0	0
T135	0	10	0	0
T136	5813	0	0	0
T137	2347	0	0	0
T138	2130	0	0	0
T139	6919	0	0	0
T140	3281	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	41006	0	0
T3	25576	172	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	0	0	0
T13	3068	0	0	0
T16	29126	0	0	0
T37	2663	0	0	0
T41	0	392	0	0
T105	0	311	0	0
T106	0	434	0	0
T107	0	34	0	0
T139	0	50	0	0
T141	0	68	0	0
T142	0	39	0	0
T143	0	18	0	0
T144	0	9	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	1180	0	0
T52	0	8	0	0
T55	140064	6	0	0
T71	0	230	0	0
T86	0	8	0	0
T95	1113	0	0	0
T96	2487	0	0	0
T98	1814	0	0	0
T99	15111	0	0	0
T100	784	0	0	0
T101	1927	0	0	0
T102	919	0	0	0
T103	36807	0	0	0
T104	2192	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	1	0	0
T148	0	11	0	0
T149	0	2	0	0
T150	0	1	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	987	0	0
T52	0	31	0	0
T71	0	201	0	0
T74	154797	4	0	0
T86	0	11	0	0
T145	0	5	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	7	0	0
T149	0	4	0	0
T150	0	6	0	0
T151	2021	0	0	0
T152	2968	0	0	0
T153	2403	0	0	0
T154	5651	0	0	0
T155	1983	0	0	0
T156	2089	0	0	0
T157	8166	0	0	0
T158	2593	0	0	0
T159	6184	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	1039	0	0
T52	0	32	0	0
T55	140064	3	0	0
T71	0	205	0	0
T72	0	10	0	0
T86	0	5	0	0
T95	1113	0	0	0
T96	2487	0	0	0
T98	1814	0	0	0
T99	15111	0	0	0
T100	784	0	0	0
T101	1927	0	0	0
T102	919	0	0	0
T103	36807	0	0	0
T104	2192	0	0	0
T145	0	4	0	0
T147	0	4	0	0
T148	0	25	0	0
T149	0	2	0	0
T150	0	8	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	1664	0	0
T52	0	28	0	0
T86	577137	7	0	0
T145	0	3	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	18	0	0
T149	0	6	0	0
T150	0	8	0	0
T160	0	7	0	0
T161	0	3	0	0
T162	1606	0	0	0
T163	5178	0	0	0
T164	33918	0	0	0
T165	1165	0	0	0
T166	22956	0	0	0
T167	1677	0	0	0
T168	6051	0	0	0
T169	54703	0	0	0
T170	4051	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503737	1023	0	0
T52	0	30	0	0
T55	140064	2	0	0
T71	0	220	0	0
T86	0	10	0	0
T95	1113	0	0	0
T96	2487	0	0	0
T98	1814	0	0	0
T99	15111	0	0	0
T100	784	0	0	0
T101	1927	0	0	0
T102	919	0	0	0
T103	36807	0	0	0
T104	2192	0	0	0
T145	0	9	0	0
T146	0	2	0	0
T147	0	9	0	0
T148	0	14	0	0
T150	0	3	0	0
T161	0	2	0	0