Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	65717226	142107	0	0
StatusRise_A	65717226	158513	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65717226	142107	0	0
T1	30324	41	0	0
T2	3957	0	0	0
T3	76728	191	0	0
T7	8808	48	0	0
T8	30063	54	0	0
T9	4146	3	0	0
T10	7005	0	0	0
T11	15057	3	0	0
T12	5304	6	0	0
T13	9204	30	0	0
T16	0	341	0	0
T37	0	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65717226	158513	0	0
T1	30324	43	0	0
T2	3957	6	0	0
T3	76728	225	0	0
T7	8808	50	0	0
T8	30063	57	0	0
T9	4146	9	0	0
T10	7005	9	0	0
T11	15057	6	0	0
T12	5304	12	0	0
T13	9204	36	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21905742	52800	0	0
StatusRise_A	21905742	58747	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	52800	0	0
T1	10108	17	0	0
T2	1319	0	0	0
T3	25576	68	0	0
T7	2936	17	0	0
T8	10021	19	0	0
T9	1382	1	0	0
T10	2335	0	0	0
T11	5019	1	0	0
T12	1768	2	0	0
T13	3068	10	0	0
T16	0	123	0	0
T37	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	58747	0	0
T1	10108	18	0	0
T2	1319	2	0	0
T3	25576	80	0	0
T7	2936	18	0	0
T8	10021	20	0	0
T9	1382	3	0	0
T10	2335	3	0	0
T11	5019	2	0	0
T12	1768	4	0	0
T13	3068	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21905742	52800	0	0
StatusRise_A	21905742	58748	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	52800	0	0
T1	10108	17	0	0
T2	1319	0	0	0
T3	25576	68	0	0
T7	2936	17	0	0
T8	10021	19	0	0
T9	1382	1	0	0
T10	2335	0	0	0
T11	5019	1	0	0
T12	1768	2	0	0
T13	3068	10	0	0
T16	0	123	0	0
T37	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	58748	0	0
T1	10108	18	0	0
T2	1319	2	0	0
T3	25576	80	0	0
T7	2936	18	0	0
T8	10021	20	0	0
T9	1382	3	0	0
T10	2335	3	0	0
T11	5019	2	0	0
T12	1768	4	0	0
T13	3068	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21905742	36507	0	0
StatusRise_A	21905742	41018	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	36507	0	0
T1	10108	7	0	0
T2	1319	0	0	0
T3	25576	55	0	0
T7	2936	14	0	0
T8	10021	16	0	0
T9	1382	1	0	0
T10	2335	0	0	0
T11	5019	1	0	0
T12	1768	2	0	0
T13	3068	10	0	0
T16	0	95	0	0
T37	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	41018	0	0
T1	10108	7	0	0
T2	1319	2	0	0
T3	25576	65	0	0
T7	2936	14	0	0
T8	10021	17	0	0
T9	1382	3	0	0
T10	2335	3	0	0
T11	5019	2	0	0
T12	1768	4	0	0
T13	3068	12	0	0