Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	21906320	5374	0	0
EscTimeoutStoppedByClReset_A	21905742	2917593	0	0
EscTimeoutTriggersReset_A	5553133	327	0	0
RomAllowActiveState_A	21905742	58372	0	0
RomAllowCheckGoodState_A	21905742	58422	0	0
RomBlockActiveState_A	21905742	28868	0	0
RomBlockCheckGoodState_A	21905742	402134	0	0
RomIntgChkDisFalse_A	21905742	21258707	0	0
RomIntgChkDisTrue_A	21905742	135983	0	0
RstreqChkEsctimeout_A	21905742	4493	0	0
RstreqChkFsmterm_A	21905742	120	0	0
RstreqChkGlbesc_A	21905742	4493	0	0
RstreqChkMainpd_A	21905742	838895	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21906320	5374	0	0
T15	15777	263	0	0
T38	66770	0	0	0
T39	15490	0	0	0
T40	11883	0	0	0
T43	15145	141	0	0
T45	2763	0	0	0
T47	3012	0	0	0
T83	3943	0	0	0
T84	3667	0	0	0
T91	0	65	0	0
T99	0	32	0	0
T171	0	12	0	0
T172	0	55	0	0
T173	0	244	0	0
T174	0	10	0	0
T175	0	44	0	0
T176	0	19	0	0
T177	4867	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	2917593	0	0
T1	10108	1494	0	0
T2	1319	7	0	0
T3	25576	2407	0	0
T7	2936	0	0	0
T8	10021	999	0	0
T9	1382	21	0	0
T10	2335	0	0	0
T11	5019	12	0	0
T12	1768	81	0	0
T13	3068	315	0	0
T16	0	3676	0	0
T37	0	268	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5553133	327	0	0
T9	226	3	0	0
T10	217	0	0	0
T11	378	0	0	0
T12	304	0	0	0
T13	488	0	0	0
T14	0	2	0	0
T15	0	3	0	0
T16	11339	0	0	0
T37	2272	0	0	0
T43	0	3	0	0
T46	392	0	0	0
T61	1127	0	0	0
T82	1661	0	0	0
T171	0	2	0	0
T172	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	5	0	0
T181	0	8	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	58372	0	0
T1	10108	18	0	0
T2	1319	2	0	0
T3	25576	80	0	0
T7	2936	18	0	0
T8	10021	20	0	0
T9	1382	3	0	0
T10	2335	3	0	0
T11	5019	2	0	0
T12	1768	4	0	0
T13	3068	12	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	58422	0	0
T1	10108	18	0	0
T2	1319	2	0	0
T3	25576	80	0	0
T7	2936	18	0	0
T8	10021	20	0	0
T9	1382	3	0	0
T10	2335	3	0	0
T11	5019	2	0	0
T12	1768	4	0	0
T13	3068	12	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	28868	0	0
T18	3974	0	0	0
T23	5621	1539	0	0
T24	20137	3	0	0
T25	0	294	0	0
T51	17081	16	0	0
T108	52121	0	0	0
T179	1784	0	0	0
T180	604	0	0	0
T182	0	638	0	0
T183	0	232	0	0
T184	0	5	0	0
T185	0	526	0	0
T186	0	6	0	0
T187	0	1421	0	0
T188	28664	0	0	0
T189	2451	0	0	0
T190	3350	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	402134	0	0
T3	25576	299	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	23	0	0
T13	3068	0	0	0
T16	29126	505	0	0
T20	0	3119	0	0
T21	0	2847	0	0
T37	2663	0	0	0
T38	0	115	0	0
T39	0	229	0	0
T41	0	550	0	0
T191	0	322	0	0
T192	0	298	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	21258707	0	0
T1	10108	10053	0	0
T2	1319	1153	0	0
T3	25576	24645	0	0
T7	2936	2867	0	0
T8	10021	9949	0	0
T9	1382	1233	0	0
T10	2335	2118	0	0
T11	5019	4927	0	0
T12	1768	1638	0	0
T13	3068	2899	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	135983	0	0
T18	3974	0	0	0
T23	5621	1568	0	0
T24	20137	1026	0	0
T25	0	287	0	0
T108	52121	0	0	0
T179	1784	0	0	0
T180	604	0	0	0
T182	0	197	0	0
T183	0	34	0	0
T185	0	1700	0	0
T186	0	208	0	0
T187	0	2310	0	0
T188	28664	0	0	0
T189	2451	0	0	0
T190	3350	0	0	0
T193	0	3719	0	0
T194	0	156	0	0
T195	1795	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	4493	0	0
T2	1319	1	0	0
T3	25576	8	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	1	0	0
T10	2335	2	0	0
T11	5019	0	0	0
T12	1768	0	0	0
T13	3068	7	0	0
T14	0	1	0	0
T16	29126	21	0	0
T37	0	6	0	0
T42	0	4	0	0
T44	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	120	0	0
T4	21364	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T26	0	40	0	0
T27	0	20	0	0
T28	3068	0	0	0
T29	27940	0	0	0
T30	11928	0	0	0
T31	4966	0	0	0
T32	1240	0	0	0
T33	5570	0	0	0
T34	8763	0	0	0
T35	2749	0	0	0
T36	6247	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	4493	0	0
T2	1319	1	0	0
T3	25576	8	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	1	0	0
T10	2335	2	0	0
T11	5019	0	0	0
T12	1768	0	0	0
T13	3068	7	0	0
T14	0	1	0	0
T16	29126	21	0	0
T37	0	6	0	0
T42	0	4	0	0
T44	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21905742	838895	0	0
T3	25576	905	0	0
T7	2936	0	0	0
T8	10021	0	0	0
T9	1382	0	0	0
T10	2335	0	0	0
T11	5019	0	0	0
T12	1768	208	0	0
T13	3068	199	0	0
T16	29126	1438	0	0
T20	0	6168	0	0
T37	2663	124	0	0
T38	0	2895	0	0
T39	0	657	0	0
T40	0	50	0	0
T41	0	3704	0	0