Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

191346

1

T1

14

T2

1

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	363968	1			T1	26		T2	1		T3	55
values[0x0]	165671	1			T1	17		T3	10		T4	32
values[0x1]	166229	1			T1	16		T3	12		T4	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	398798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

297070

1

T1

14

T2

1

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2558	1			T3	8		T4	3		T7	2
valid_sources[0x01]	1878	1			T7	1		T8	2		T23	1
valid_sources[0x02]	1908	1			T7	1		T10	2		T42	1
valid_sources[0x03]	3282	1			T10	2		T23	1		T79	2
valid_sources[0x04]	2175	1			T4	2		T23	2		T15	1
valid_sources[0x05]	2356	1			T8	1		T189	1		T16	2
valid_sources[0x06]	1935	1			T8	1		T23	1		T16	1
valid_sources[0x07]	2589	1			T23	3		T46	1		T16	2
valid_sources[0x08]	2088	1			T7	1		T8	1		T23	2
valid_sources[0x09]	5068	1			T23	1		T41	1		T16	1
valid_sources[0x0a]	9369	1			T7	2		T8	1		T10	7
valid_sources[0x0b]	2071	1			T7	1		T8	2		T12	4
valid_sources[0x0c]	2190	1			T4	2		T8	1		T13	28
valid_sources[0x0d]	2073	1			T13	5		T189	3		T58	2
valid_sources[0x0e]	2157	1			T23	1		T16	1		T58	6
valid_sources[0x0f]	2142	1			T4	1		T7	3		T23	2
valid_sources[0x10]	4211	1			T23	2		T189	2		T24	10
valid_sources[0x11]	2112	1			T23	4		T189	1		T58	1
valid_sources[0x12]	2029	1			T4	2		T15	1		T41	2
valid_sources[0x13]	2097	1			T16	2		T25	13		T62	1
valid_sources[0x14]	1835	1			T23	2		T42	1		T16	1
valid_sources[0x15]	1879	1			T4	4		T15	4		T189	8
valid_sources[0x16]	3863	1			T4	1		T23	2		T40	1
valid_sources[0x17]	2608	1			T7	2		T8	2		T12	1
valid_sources[0x18]	4655	1			T23	2		T16	1		T25	12
valid_sources[0x19]	3969	1			T23	2		T41	5		T189	3
valid_sources[0x1a]	2604	1			T4	3		T13	12		T23	4
valid_sources[0x1b]	2364	1			T23	2		T58	2		T25	25
valid_sources[0x1c]	2215	1			T4	3		T15	2		T42	1
valid_sources[0x1d]	2179	1			T8	1		T23	1		T40	4
valid_sources[0x1e]	3259	1			T23	1		T42	1		T16	1
valid_sources[0x1f]	2407	1			T12	2		T23	1		T45	1
valid_sources[0x20]	3756	1			T7	1		T10	7		T189	2
valid_sources[0x21]	2483	1			T7	1		T23	2		T24	5
valid_sources[0x22]	2715	1			T15	1		T189	3		T24	5
valid_sources[0x23]	2812	1			T15	1		T42	1		T58	2
valid_sources[0x24]	2799	1			T1	12		T3	1		T81	2
valid_sources[0x25]	2631	1			T3	6		T15	3		T41	1
valid_sources[0x26]	3043	1			T7	1		T23	1		T40	1
valid_sources[0x27]	1990	1			T7	1		T23	1		T189	4
valid_sources[0x28]	2145	1			T4	1		T10	1		T15	1
valid_sources[0x29]	1958	1			T8	2		T23	2		T58	2
valid_sources[0x2a]	3822	1			T12	1		T189	2		T46	1
valid_sources[0x2b]	6531	1			T12	2		T13	3		T23	5
valid_sources[0x2c]	2047	1			T4	1		T23	2		T45	1
valid_sources[0x2d]	2144	1			T4	1		T42	2		T79	1
valid_sources[0x2e]	2720	1			T16	1		T82	5		T86	4
valid_sources[0x2f]	1980	1			T8	1		T40	2		T15	1
valid_sources[0x30]	2128	1			T23	1		T41	5		T16	1
valid_sources[0x31]	4096	1			T4	1		T23	1		T189	2
valid_sources[0x32]	5805	1			T8	1		T23	1		T15	1
valid_sources[0x33]	2005	1			T4	8		T12	1		T23	1
valid_sources[0x34]	4593	1			T4	1		T10	5		T23	5
valid_sources[0x35]	3120	1			T4	4		T8	1		T23	3
valid_sources[0x36]	2061	1			T4	1		T12	1		T23	1
valid_sources[0x37]	1960	1			T4	3		T7	1		T10	1
valid_sources[0x38]	2393	1			T7	2		T12	2		T23	1
valid_sources[0x39]	3180	1			T61	1		T46	1		T16	1
valid_sources[0x3a]	2947	1			T4	3		T7	2		T10	6
valid_sources[0x3b]	2758	1			T4	1		T23	1		T58	3
valid_sources[0x3c]	3321	1			T4	3		T23	3		T189	3
valid_sources[0x3d]	2672	1			T3	2		T8	1		T14	25
valid_sources[0x3e]	2117	1			T3	1		T10	7		T23	1
valid_sources[0x3f]	2117	1			T4	4		T7	1		T23	1
valid_sources[0x40]	1825	1			T7	2		T23	1		T15	1
valid_sources[0x41]	3830	1			T4	3		T61	4		T58	1
valid_sources[0x42]	2514	1			T23	2		T189	1		T81	2
valid_sources[0x43]	3208	1			T4	5		T10	6		T23	2
valid_sources[0x44]	3703	1			T23	3		T15	1		T189	4
valid_sources[0x45]	1947	1			T4	4		T23	2		T41	2
valid_sources[0x46]	6294	1			T4	2		T12	1		T23	1
valid_sources[0x47]	2016	1			T23	1		T15	1		T16	1
valid_sources[0x48]	1998	1			T3	1		T40	4		T16	3
valid_sources[0x49]	2120	1			T7	1		T23	2		T45	1
valid_sources[0x4a]	2953	1			T12	3		T40	10		T42	1
valid_sources[0x4b]	2902	1			T23	1		T16	2		T81	1
valid_sources[0x4c]	5389	1			T8	1		T24	3003		T58	1
valid_sources[0x4d]	2317	1			T4	2		T8	1		T23	1
valid_sources[0x4e]	2215	1			T15	2		T42	1		T24	5
valid_sources[0x4f]	1981	1			T1	1		T23	1		T189	3
valid_sources[0x50]	2223	1			T10	6		T23	5		T15	1
valid_sources[0x51]	2062	1			T23	1		T189	1		T16	1
valid_sources[0x52]	1966	1			T79	3		T82	2		T86	16
valid_sources[0x53]	2114	1			T23	1		T46	1		T24	5
valid_sources[0x54]	2065	1			T3	4		T13	13		T23	1
valid_sources[0x55]	2155	1			T4	3		T23	2		T45	1
valid_sources[0x56]	2186	1			T4	10		T7	2		T16	1
valid_sources[0x57]	2309	1			T4	3		T7	1		T23	2
valid_sources[0x58]	2134	1			T4	1		T8	1		T45	5
valid_sources[0x59]	7131	1			T7	1		T12	1		T40	3
valid_sources[0x5a]	1930	1			T23	2		T189	1		T42	3
valid_sources[0x5b]	3210	1			T23	1		T41	3		T189	5
valid_sources[0x5c]	4226	1			T8	1		T10	8		T23	1
valid_sources[0x5d]	2162	1			T8	1		T15	4		T16	1
valid_sources[0x5e]	3264	1			T4	2		T23	3		T15	1
valid_sources[0x5f]	4120	1			T23	1		T189	7		T16	1
valid_sources[0x60]	2233	1			T8	1		T189	1		T42	2
valid_sources[0x61]	1815	1			T4	11		T8	1		T42	1
valid_sources[0x62]	2291	1			T10	1		T23	3		T24	5
valid_sources[0x63]	2580	1			T23	7		T16	4		T24	5
valid_sources[0x64]	3605	1			T7	1		T189	3		T58	3
valid_sources[0x65]	1985	1			T8	1		T23	3		T189	4
valid_sources[0x66]	4640	1			T3	1		T45	1		T16	2
valid_sources[0x67]	3665	1			T4	1		T8	1		T10	5
valid_sources[0x68]	2192	1			T4	2		T23	4		T16	2
valid_sources[0x69]	3043	1			T7	1		T189	2		T42	1
valid_sources[0x6a]	1900	1			T4	1		T10	5		T23	1
valid_sources[0x6b]	2160	1			T7	2		T23	2		T41	3
valid_sources[0x6c]	2028	1			T41	3		T189	1		T42	2
valid_sources[0x6d]	4436	1			T1	3		T7	1		T10	11
valid_sources[0x6e]	3773	1			T23	1		T42	1		T16	2
valid_sources[0x6f]	1973	1			T23	1		T40	5		T46	1
valid_sources[0x70]	4076	1			T3	4		T23	5		T15	4
valid_sources[0x71]	2201	1			T7	1		T80	2		T24	15
valid_sources[0x72]	2169	1			T8	4		T40	2		T15	1
valid_sources[0x73]	1890	1			T4	3		T16	1		T86	8
valid_sources[0x74]	2020	1			T189	2		T16	1		T24	10
valid_sources[0x75]	2285	1			T23	1		T58	1		T81	1
valid_sources[0x76]	3172	1			T23	1		T16	2		T25	1140
valid_sources[0x77]	2137	1			T23	2		T16	4		T58	1
valid_sources[0x78]	2000	1			T2	1		T23	1		T189	5
valid_sources[0x79]	2109	1			T8	1		T23	1		T15	1
valid_sources[0x7a]	2674	1			T4	4		T8	2		T189	7
valid_sources[0x7b]	2235	1			T16	1		T58	5		T79	1
valid_sources[0x7c]	3687	1			T3	4		T24	10		T58	1
valid_sources[0x7d]	2065	1			T15	4		T24	5		T82	11
valid_sources[0x7e]	3990	1			T7	1		T189	4		T16	2
valid_sources[0x7f]	2291	1			T7	1		T8	1		T13	12
valid_sources[0x80]	3325	1			T7	1		T23	2		T45	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

95993

1

T1

10

T2

1

T3

16

values[0x0]

all_enables

biggest_size

61607

1

T1

3

T3

1

T4

11

values[0x1]

all_enables

biggest_size

33746

1

T1

1

T3

2

T4

8