SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35192 | 1 | T3 | 1 | T82 | 416 | T183 | 402 | ||||
others[1] | 35020 | 1 | T27 | 1 | T82 | 416 | T183 | 408 | ||||
others[2] | 34883 | 1 | T3 | 1 | T27 | 1 | T82 | 395 | ||||
others[3] | 58202 | 1 | T82 | 644 | T183 | 670 | T47 | 669 | ||||
false | 18466 | 1 | T3 | 2 | T12 | 6 | T13 | 58 | ||||
true | 28439 | 1 | T1 | 13 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35024 | 1 | T82 | 380 | T183 | 400 | T47 | 393 | ||||
others[1] | 35108 | 1 | T27 | 1 | T82 | 406 | T183 | 394 | ||||
others[2] | 35059 | 1 | T3 | 2 | T82 | 410 | T183 | 420 | ||||
others[3] | 58213 | 1 | T82 | 664 | T183 | 663 | T47 | 616 | ||||
false | 11832 | 1 | T3 | 2 | T12 | 3 | T13 | 29 | ||||
true | 21871 | 1 | T1 | 13 | T2 | 2 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 726 | 1 | T3 | 1 | T4 | 8 | T6 | 1 | ||||
others[1] | 686 | 1 | T3 | 1 | T4 | 3 | T13 | 1 | ||||
others[2] | 699 | 1 | T3 | 1 | T4 | 6 | T13 | 2 | ||||
others[3] | 1183 | 1 | T1 | 2 | T4 | 4 | T6 | 2 | ||||
false | 13826 | 1 | T1 | 19 | T2 | 2 | T3 | 6 | ||||
true | 4199 | 1 | T1 | 4 | T3 | 2 | T4 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |