Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T12,T13

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24498855	5933	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24498855	258126	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24498855	10017815	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24498855	258121	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24498855	5933	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24498855	258126	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24498855	10017815	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24498855	258121	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	5933	0	0
T11	727	0	0	0
T12	2046	2	0	0
T13	110608	11	0	0
T14	3126	2	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	75	0	0
T25	0	76	0	0
T39	4196	0	0	0
T40	5023	4	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T61	0	1	0	0
T79	0	8	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	258126	0	0
T11	727	0	0	0
T12	2046	98	0	0
T13	110608	574	0	0
T14	3126	439	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	5807	0	0
T25	0	2027	0	0
T39	4196	0	0	0
T40	5023	309	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	155	0	0
T46	0	492	0	0
T61	0	14	0	0
T79	0	304	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	10017815	0	0
T8	3008	2045	0	0
T9	2334	0	0	0
T10	9369	6045	0	0
T11	727	0	0	0
T12	2046	751	0	0
T13	110608	48945	0	0
T14	3126	727	0	0
T15	0	865	0	0
T23	19712	9210	0	0
T39	4196	0	0	0
T40	0	3745	0	0
T44	1988	0	0	0
T45	0	813	0	0
T80	0	749	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	258121	0	0
T11	727	0	0	0
T12	2046	95	0	0
T13	110608	574	0	0
T14	3126	439	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	5810	0	0
T25	0	2034	0	0
T39	4196	0	0	0
T40	5023	309	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	155	0	0
T46	0	492	0	0
T61	0	14	0	0
T79	0	304	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	5933	0	0
T11	727	0	0	0
T12	2046	2	0	0
T13	110608	11	0	0
T14	3126	2	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	75	0	0
T25	0	76	0	0
T39	4196	0	0	0
T40	5023	4	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T61	0	1	0	0
T79	0	8	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	258126	0	0
T11	727	0	0	0
T12	2046	98	0	0
T13	110608	574	0	0
T14	3126	439	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	5807	0	0
T25	0	2027	0	0
T39	4196	0	0	0
T40	5023	309	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	155	0	0
T46	0	492	0	0
T61	0	14	0	0
T79	0	304	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	10017815	0	0
T8	3008	2045	0	0
T9	2334	0	0	0
T10	9369	6045	0	0
T11	727	0	0	0
T12	2046	751	0	0
T13	110608	48945	0	0
T14	3126	727	0	0
T15	0	865	0	0
T23	19712	9210	0	0
T39	4196	0	0	0
T40	0	3745	0	0
T44	1988	0	0	0
T45	0	813	0	0
T80	0	749	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	258121	0	0
T11	727	0	0	0
T12	2046	95	0	0
T13	110608	574	0	0
T14	3126	439	0	0
T17	875	0	0	0
T23	19712	0	0	0
T24	0	5810	0	0
T25	0	2034	0	0
T39	4196	0	0	0
T40	5023	309	0	0
T43	15258	0	0	0
T44	1988	0	0	0
T45	0	155	0	0
T46	0	492	0	0
T61	0	14	0	0
T79	0	304	0	0