Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25086049	15254	0	0
intr_enable_rd_A	25086049	33765	0	0
reset_en_rd_A	25086049	1341	0	0
reset_en_regwen_rd_A	25086049	1092	0	0
wake_info_capture_dis_rd_A	25086049	1153	0	0
wakeup_en_rd_A	25086049	2163	0	0
wakeup_en_regwen_rd_A	25086049	1122	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	15254	0	0
T24	405078	89	0	0
T25	299850	7	0	0
T26	0	5	0	0
T51	0	68	0	0
T58	4897	0	0	0
T62	16215	0	0	0
T73	0	9	0	0
T79	12745	0	0	0
T81	5429	0	0	0
T82	15724	0	0	0
T85	14954	0	0	0
T86	40890	0	0	0
T87	1892	0	0	0
T136	0	22	0	0
T137	0	13	0	0
T138	0	12	0	0
T139	0	37	0	0
T140	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	33765	0	0
T4	4370	105	0	0
T5	15130	0	0	0
T6	1942	0	0	0
T7	4280	0	0	0
T8	3008	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	2046	0	0	0
T13	110608	472	0	0
T14	3126	0	0	0
T31	0	43	0	0
T34	0	48	0	0
T141	0	69	0	0
T142	0	9	0	0
T143	0	51	0	0
T144	0	179	0	0
T145	0	188	0	0
T146	0	167	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	1341	0	0
T74	0	5	0	0
T84	0	6	0	0
T108	2056	0	0	0
T138	474928	7	0	0
T147	0	5	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	2	0	0
T151	0	6	0	0
T152	0	15	0	0
T153	0	16	0	0
T154	4021	0	0	0
T155	19960	0	0	0
T156	3700	0	0	0
T157	5139	0	0	0
T158	18620	0	0	0
T159	9773	0	0	0
T160	6164	0	0	0
T161	16127	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	1092	0	0
T49	0	34	0	0
T74	0	3	0	0
T108	2056	0	0	0
T138	474928	5	0	0
T147	0	2	0	0
T148	0	13	0	0
T149	0	11	0	0
T150	0	1	0	0
T151	0	4	0	0
T152	0	4	0	0
T153	0	10	0	0
T154	4021	0	0	0
T155	19960	0	0	0
T156	3700	0	0	0
T157	5139	0	0	0
T158	18620	0	0	0
T159	9773	0	0	0
T160	6164	0	0	0
T161	16127	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	1153	0	0
T49	0	55	0	0
T60	0	2	0	0
T74	0	2	0	0
T84	0	1	0	0
T108	2056	0	0	0
T138	474928	10	0	0
T147	0	6	0	0
T148	0	11	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	26	0	0
T154	4021	0	0	0
T155	19960	0	0	0
T156	3700	0	0	0
T157	5139	0	0	0
T158	18620	0	0	0
T159	9773	0	0	0
T160	6164	0	0	0
T161	16127	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	2163	0	0
T26	222578	5	0	0
T38	6756	0	0	0
T49	0	150	0	0
T60	0	3	0	0
T84	0	5	0	0
T106	11960	0	0	0
T147	0	7	0	0
T148	0	5	0	0
T150	0	3	0	0
T151	0	7	0	0
T152	0	12	0	0
T153	0	3	0	0
T162	1233	0	0	0
T163	1500	0	0	0
T164	16605	0	0	0
T165	4020	0	0	0
T166	9063	0	0	0
T167	2127	0	0	0
T168	7063	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25086049	1122	0	0
T49	0	31	0	0
T74	0	8	0	0
T84	0	10	0	0
T108	2056	0	0	0
T138	474928	2	0	0
T147	0	7	0	0
T148	0	7	0	0
T150	0	8	0	0
T151	0	6	0	0
T152	0	16	0	0
T153	0	7	0	0
T154	4021	0	0	0
T155	19960	0	0	0
T156	3700	0	0	0
T157	5139	0	0	0
T158	18620	0	0	0
T159	9773	0	0	0
T160	6164	0	0	0
T161	16127	0	0	0