Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73496565	143241	0	0
StatusRise_A	73496565	159951	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73496565	143241	0	0
T1	9309	54	0	0
T2	2604	0	0	0
T3	15423	18	0	0
T4	13110	9	0	0
T5	45390	3	0	0
T6	5826	30	0	0
T7	12840	54	0	0
T8	9024	15	0	0
T9	7002	3	0	0
T10	28107	22	0	0
T14	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73496565	159951	0	0
T1	9309	60	0	0
T2	2604	6	0	0
T3	15423	21	0	0
T4	13110	12	0	0
T5	45390	6	0	0
T6	5826	33	0	0
T7	12840	57	0	0
T8	9024	17	0	0
T9	7002	9	0	0
T10	28107	25	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24498855	53132	0	0
StatusRise_A	24498855	59166	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	53132	0	0
T1	3103	18	0	0
T2	868	0	0	0
T3	5141	6	0	0
T4	4370	3	0	0
T5	15130	1	0	0
T6	1942	10	0	0
T7	4280	18	0	0
T8	3008	6	0	0
T9	2334	1	0	0
T10	9369	9	0	0
T14	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	59166	0	0
T1	3103	20	0	0
T2	868	2	0	0
T3	5141	7	0	0
T4	4370	4	0	0
T5	15130	2	0	0
T6	1942	11	0	0
T7	4280	19	0	0
T8	3008	7	0	0
T9	2334	3	0	0
T10	9369	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24498855	53133	0	0
StatusRise_A	24498855	59166	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	53133	0	0
T1	3103	18	0	0
T2	868	0	0	0
T3	5141	6	0	0
T4	4370	3	0	0
T5	15130	1	0	0
T6	1942	10	0	0
T7	4280	18	0	0
T8	3008	6	0	0
T9	2334	1	0	0
T10	9369	9	0	0
T14	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	59166	0	0
T1	3103	20	0	0
T2	868	2	0	0
T3	5141	7	0	0
T4	4370	4	0	0
T5	15130	2	0	0
T6	1942	11	0	0
T7	4280	19	0	0
T8	3008	7	0	0
T9	2334	3	0	0
T10	9369	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24498855	36976	0	0
StatusRise_A	24498855	41619	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	36976	0	0
T1	3103	18	0	0
T2	868	0	0	0
T3	5141	6	0	0
T4	4370	3	0	0
T5	15130	1	0	0
T6	1942	10	0	0
T7	4280	18	0	0
T8	3008	3	0	0
T9	2334	1	0	0
T10	9369	4	0	0
T14	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	41619	0	0
T1	3103	20	0	0
T2	868	2	0	0
T3	5141	7	0	0
T4	4370	4	0	0
T5	15130	2	0	0
T6	1942	11	0	0
T7	4280	19	0	0
T8	3008	3	0	0
T9	2334	3	0	0
T10	9369	5	0	0