Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24499445	5214	0	0
EscTimeoutStoppedByClReset_A	24498855	3516886	0	0
EscTimeoutTriggersReset_A	4838207	322	0	0
RomAllowActiveState_A	24498855	58780	0	0
RomAllowCheckGoodState_A	24498855	58830	0	0
RomBlockActiveState_A	24498855	22057	0	0
RomBlockCheckGoodState_A	24498855	419605	0	0
RomIntgChkDisFalse_A	24498855	23828275	0	0
RomIntgChkDisTrue_A	24498855	151227	0	0
RstreqChkEsctimeout_A	24498855	4578	0	0
RstreqChkFsmterm_A	24498855	160	0	0
RstreqChkGlbesc_A	24498855	4578	0	0
RstreqChkMainpd_A	24498855	975579	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24499445	5214	0	0
T5	15130	142	0	0
T6	1943	0	0	0
T7	4280	0	0	0
T8	3009	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	2047	0	0	0
T13	110609	0	0	0
T14	3127	0	0	0
T23	19712	0	0	0
T35	0	14	0	0
T43	0	31	0	0
T85	0	55	0	0
T87	0	17	0	0
T91	0	156	0	0
T169	0	56	0	0
T170	0	8	0	0
T171	0	22	0	0
T172	0	1	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	3516886	0	0
T1	3103	327	0	0
T2	868	15	0	0
T3	5141	216	0	0
T4	4370	35	0	0
T5	15130	31	0	0
T6	1942	197	0	0
T7	4280	373	0	0
T8	3008	208	0	0
T9	2334	34	0	0
T10	9369	1113	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4838207	322	0	0
T5	350	3	0	0
T6	563	0	0	0
T7	829	0	0	0
T8	1062	0	0	0
T9	198	3	0	0
T10	910	0	0	0
T11	0	6	0	0
T12	786	0	0	0
T13	10900	0	0	0
T14	305	0	0	0
T23	2170	0	0	0
T35	0	3	0	0
T43	0	2	0	0
T85	0	3	0	0
T87	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T169	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	58780	0	0
T1	3103	13	0	0
T2	868	2	0	0
T3	5141	7	0	0
T4	4370	4	0	0
T5	15130	2	0	0
T6	1942	11	0	0
T7	4280	12	0	0
T8	3008	7	0	0
T9	2334	3	0	0
T10	9369	10	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	58830	0	0
T1	3103	14	0	0
T2	868	2	0	0
T3	5141	7	0	0
T4	4370	4	0	0
T5	15130	2	0	0
T6	1942	11	0	0
T7	4280	13	0	0
T8	3008	7	0	0
T9	2334	3	0	0
T10	9369	10	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	22057	0	0
T3	5141	1472	0	0
T4	4370	0	0	0
T5	15130	0	0	0
T6	1942	0	0	0
T7	4280	0	0	0
T8	3008	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	2046	0	0	0
T14	3126	0	0	0
T27	0	596	0	0
T28	0	95	0	0
T36	0	1394	0	0
T47	0	7	0	0
T90	0	61	0	0
T105	0	10	0	0
T165	0	495	0	0
T173	0	608	0	0
T174	0	37	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	419605	0	0
T3	5141	822	0	0
T4	4370	0	0	0
T5	15130	0	0	0
T6	1942	0	0	0
T7	4280	0	0	0
T8	3008	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	2046	69	0	0
T13	0	664	0	0
T14	3126	0	0	0
T24	0	2545	0	0
T25	0	2848	0	0
T27	0	442	0	0
T40	0	69	0	0
T79	0	436	0	0
T82	0	750	0	0
T86	0	46	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	23828275	0	0
T1	3103	2227	0	0
T2	868	717	0	0
T3	5141	3401	0	0
T4	4370	4298	0	0
T5	15130	15068	0	0
T6	1942	1885	0	0
T7	4280	3374	0	0
T8	3008	2926	0	0
T9	2334	2216	0	0
T10	9369	9311	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	151227	0	0
T3	5141	1644	0	0
T4	4370	0	0	0
T5	15130	0	0	0
T6	1942	0	0	0
T7	4280	0	0	0
T8	3008	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	2046	0	0	0
T14	3126	0	0	0
T27	0	157	0	0
T28	0	58	0	0
T36	0	399	0	0
T37	0	2009	0	0
T90	0	372	0	0
T146	0	320	0	0
T173	0	1032	0	0
T174	0	370	0	0
T175	0	897	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	4578	0	0
T1	3103	5	0	0
T2	868	1	0	0
T3	5141	1	0	0
T4	4370	0	0	0
T5	15130	1	0	0
T6	1942	6	0	0
T7	4280	4	0	0
T8	3008	0	0	0
T9	2334	1	0	0
T10	9369	0	0	0
T11	0	1	0	0
T13	0	8	0	0
T39	0	8	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	160	0	0
T20	39831	40	0	0
T21	0	20	0	0
T22	0	40	0	0
T26	222578	0	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	5515	0	0	0
T32	3133	0	0	0
T33	3018	0	0	0
T34	4297	0	0	0
T35	1370	0	0	0
T36	5035	0	0	0
T37	57311	0	0	0
T38	6756	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	4578	0	0
T1	3103	5	0	0
T2	868	1	0	0
T3	5141	1	0	0
T4	4370	0	0	0
T5	15130	1	0	0
T6	1942	6	0	0
T7	4280	4	0	0
T8	3008	0	0	0
T9	2334	1	0	0
T10	9369	0	0	0
T11	0	1	0	0
T13	0	8	0	0
T39	0	8	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24498855	975579	0	0
T1	3103	171	0	0
T2	868	0	0	0
T3	5141	714	0	0
T4	4370	0	0	0
T5	15130	0	0	0
T6	1942	75	0	0
T7	4280	117	0	0
T8	3008	0	0	0
T9	2334	0	0	0
T10	9369	0	0	0
T12	0	168	0	0
T13	0	2277	0	0
T17	0	6	0	0
T39	0	400	0	0
T40	0	192	0	0
T41	0	142	0	0