Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	557177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

211030

1

T1

193

T2

2594

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	401338	1			T1	431		T2	4823		T3	1
values[0x0]	182944	1			T1	226		T2	2747		T4	13
values[0x1]	183925	1			T1	226		T2	2732		T4	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	440833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

327374

1

T1

347

T2

4155

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4458	1			T1	4		T2	40		T5	25
valid_sources[0x01]	2433	1			T1	1		T2	53		T7	6
valid_sources[0x02]	2378	1			T2	25		T7	9		T55	156
valid_sources[0x03]	3077	1			T2	47		T7	3		T32	3
valid_sources[0x04]	3634	1			T1	7		T2	26		T7	5
valid_sources[0x05]	2312	1			T1	1		T2	38		T7	3
valid_sources[0x06]	2755	1			T1	4		T2	49		T7	3
valid_sources[0x07]	4048	1			T1	1		T2	31		T5	13
valid_sources[0x08]	3669	1			T1	4		T2	41		T7	6
valid_sources[0x09]	2631	1			T1	9		T2	45		T7	1
valid_sources[0x0a]	2651	1			T1	2		T2	50		T5	12
valid_sources[0x0b]	2875	1			T2	36		T7	11		T32	7
valid_sources[0x0c]	2504	1			T1	1		T2	35		T7	3
valid_sources[0x0d]	2870	1			T1	9		T2	32		T5	2
valid_sources[0x0e]	2497	1			T1	1		T2	34		T4	1
valid_sources[0x0f]	2772	1			T1	2		T2	19		T7	2
valid_sources[0x10]	2618	1			T1	7		T2	35		T5	12
valid_sources[0x11]	3019	1			T1	5		T2	29		T7	1
valid_sources[0x12]	2637	1			T1	5		T2	43		T4	1
valid_sources[0x13]	3849	1			T1	1		T2	58		T7	1
valid_sources[0x14]	2653	1			T1	6		T2	26		T7	1
valid_sources[0x15]	3397	1			T1	4		T2	21		T5	20
valid_sources[0x16]	2404	1			T1	1		T2	35		T5	3
valid_sources[0x17]	3138	1			T2	48		T7	3		T32	3
valid_sources[0x18]	6252	1			T2	29		T4	1		T7	8
valid_sources[0x19]	2594	1			T1	2		T2	33		T5	15
valid_sources[0x1a]	3775	1			T1	1		T2	48		T7	12
valid_sources[0x1b]	3145	1			T1	7		T2	48		T5	4
valid_sources[0x1c]	2760	1			T2	36		T7	2		T32	8
valid_sources[0x1d]	2394	1			T2	38		T7	8		T32	4
valid_sources[0x1e]	2753	1			T1	7		T2	44		T5	8
valid_sources[0x1f]	2718	1			T1	3		T2	29		T5	14
valid_sources[0x20]	2375	1			T1	1		T2	56		T7	3
valid_sources[0x21]	2747	1			T1	1		T2	37		T5	1
valid_sources[0x22]	2361	1			T1	2		T2	26		T5	1
valid_sources[0x23]	3676	1			T1	5		T2	61		T5	46
valid_sources[0x24]	2228	1			T1	1		T2	36		T5	2
valid_sources[0x25]	3189	1			T1	4		T2	54		T7	4
valid_sources[0x26]	2326	1			T1	1		T2	40		T7	10
valid_sources[0x27]	7638	1			T1	9		T2	32		T7	2
valid_sources[0x28]	2803	1			T1	9		T2	29		T5	3
valid_sources[0x29]	2738	1			T1	7		T2	26		T5	2
valid_sources[0x2a]	2553	1			T2	42		T4	1		T7	1
valid_sources[0x2b]	2462	1			T2	31		T4	3		T5	8
valid_sources[0x2c]	3964	1			T1	6		T2	32		T78	1
valid_sources[0x2d]	2275	1			T2	51		T5	7		T7	1
valid_sources[0x2e]	2532	1			T1	2		T2	41		T5	5
valid_sources[0x2f]	2452	1			T1	3		T2	44		T7	2
valid_sources[0x30]	3089	1			T1	2		T2	38		T7	3
valid_sources[0x31]	5878	1			T1	5		T2	45		T5	3
valid_sources[0x32]	2687	1			T2	37		T7	1		T78	2
valid_sources[0x33]	5342	1			T1	2		T2	45		T4	1
valid_sources[0x34]	2355	1			T1	16		T2	45		T7	2
valid_sources[0x35]	2647	1			T1	3		T2	31		T7	1
valid_sources[0x36]	2379	1			T1	1		T2	41		T7	4
valid_sources[0x37]	2389	1			T1	8		T2	37		T4	5
valid_sources[0x38]	4826	1			T1	7		T2	56		T7	6
valid_sources[0x39]	2397	1			T1	9		T2	30		T4	2
valid_sources[0x3a]	3172	1			T1	3		T2	45		T5	1
valid_sources[0x3b]	2554	1			T2	47		T7	4		T78	1
valid_sources[0x3c]	2437	1			T1	6		T2	29		T5	1
valid_sources[0x3d]	2398	1			T1	4		T2	23		T7	1
valid_sources[0x3e]	2788	1			T1	7		T2	40		T7	17
valid_sources[0x3f]	2922	1			T1	2		T2	64		T7	2
valid_sources[0x40]	2888	1			T1	2		T2	54		T7	13
valid_sources[0x41]	4320	1			T1	3		T2	39		T4	1
valid_sources[0x42]	2358	1			T1	4		T2	33		T7	3
valid_sources[0x43]	3228	1			T1	4		T2	34		T5	5
valid_sources[0x44]	2376	1			T1	7		T2	44		T7	2
valid_sources[0x45]	3869	1			T1	1		T2	39		T5	11
valid_sources[0x46]	2808	1			T1	11		T2	43		T7	5
valid_sources[0x47]	2390	1			T1	5		T2	42		T4	2
valid_sources[0x48]	2828	1			T1	2		T2	48		T7	4
valid_sources[0x49]	2922	1			T2	47		T5	1		T7	3
valid_sources[0x4a]	2834	1			T1	2		T2	45		T5	1
valid_sources[0x4b]	2233	1			T1	2		T2	27		T7	5
valid_sources[0x4c]	2182	1			T1	2		T2	66		T7	1
valid_sources[0x4d]	2945	1			T2	48		T5	9		T32	2
valid_sources[0x4e]	2442	1			T1	4		T2	47		T5	5
valid_sources[0x4f]	2462	1			T2	33		T7	5		T32	3
valid_sources[0x50]	2655	1			T1	4		T2	55		T7	5
valid_sources[0x51]	4231	1			T1	4		T2	39		T5	3
valid_sources[0x52]	2755	1			T1	2		T2	43		T7	2
valid_sources[0x53]	2600	1			T1	5		T2	39		T7	4
valid_sources[0x54]	2429	1			T1	6		T2	49		T4	3
valid_sources[0x55]	2733	1			T1	6		T2	35		T7	3
valid_sources[0x56]	2495	1			T1	8		T2	23		T4	1
valid_sources[0x57]	2274	1			T1	2		T2	33		T7	2
valid_sources[0x58]	2677	1			T1	1		T2	39		T7	4
valid_sources[0x59]	2727	1			T2	24		T4	2		T5	10
valid_sources[0x5a]	2425	1			T1	3		T2	46		T7	5
valid_sources[0x5b]	2623	1			T1	14		T2	30		T5	1
valid_sources[0x5c]	2306	1			T2	54		T5	20		T7	1
valid_sources[0x5d]	2827	1			T1	2		T2	31		T5	5
valid_sources[0x5e]	2527	1			T1	3		T2	33		T78	1
valid_sources[0x5f]	2453	1			T1	1		T2	75		T5	2
valid_sources[0x60]	2822	1			T1	8		T2	35		T7	1
valid_sources[0x61]	2490	1			T1	3		T2	42		T5	1
valid_sources[0x62]	3980	1			T1	2		T2	36		T7	1
valid_sources[0x63]	3041	1			T1	2		T2	33		T4	1
valid_sources[0x64]	2262	1			T2	34		T5	1		T7	5
valid_sources[0x65]	3767	1			T1	8		T2	37		T5	3
valid_sources[0x66]	3746	1			T2	50		T7	1		T32	3
valid_sources[0x67]	3076	1			T2	35		T7	6		T78	2
valid_sources[0x68]	3116	1			T1	7		T2	24		T7	1
valid_sources[0x69]	2638	1			T1	4		T2	65		T4	1
valid_sources[0x6a]	2336	1			T1	5		T2	45		T5	17
valid_sources[0x6b]	2403	1			T1	5		T2	41		T7	2
valid_sources[0x6c]	2682	1			T2	36		T7	2		T32	6
valid_sources[0x6d]	2494	1			T1	10		T2	24		T4	2
valid_sources[0x6e]	3415	1			T1	3		T2	39		T4	3
valid_sources[0x6f]	2775	1			T1	4		T2	39		T7	5
valid_sources[0x70]	2301	1			T1	1		T2	52		T4	1
valid_sources[0x71]	2714	1			T1	9		T2	32		T5	15
valid_sources[0x72]	2318	1			T1	2		T2	37		T5	16
valid_sources[0x73]	2335	1			T1	1		T2	39		T7	2
valid_sources[0x74]	3233	1			T1	4		T2	23		T4	1
valid_sources[0x75]	2423	1			T1	4		T2	43		T32	1
valid_sources[0x76]	2346	1			T1	1		T2	26		T32	4
valid_sources[0x77]	2399	1			T1	1		T2	28		T7	7
valid_sources[0x78]	2724	1			T1	7		T2	24		T5	15
valid_sources[0x79]	2662	1			T1	4		T2	27		T4	1
valid_sources[0x7a]	3548	1			T2	41		T5	9		T7	7
valid_sources[0x7b]	2514	1			T2	33		T5	8		T7	12
valid_sources[0x7c]	13257	1			T1	7		T2	43		T5	6
valid_sources[0x7d]	2770	1			T1	1		T2	36		T4	9
valid_sources[0x7e]	3128	1			T2	31		T7	2		T78	1
valid_sources[0x7f]	2677	1			T1	6		T2	46		T7	2
valid_sources[0x80]	2198	1			T2	72		T7	10		T78	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

106537

1

T1

84

T2

1143

T3

1

values[0x0]

all_enables

biggest_size

67912

1

T1

78

T2

963

T4

2

values[0x1]

all_enables

biggest_size

36581

1

T1

31

T2

488

T4

5