SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34967 | 1 | T1 | 312 | T5 | 388 | T19 | 1 | ||||
others[1] | 35082 | 1 | T1 | 292 | T5 | 432 | T19 | 1 | ||||
others[2] | 34927 | 1 | T1 | 282 | T5 | 394 | T32 | 389 | ||||
others[3] | 58339 | 1 | T1 | 524 | T5 | 649 | T32 | 700 | ||||
false | 20261 | 1 | T1 | 50 | T2 | 352 | T5 | 50 | ||||
true | 30864 | 1 | T1 | 52 | T2 | 454 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34794 | 1 | T1 | 308 | T5 | 383 | T32 | 404 | ||||
others[1] | 34806 | 1 | T1 | 299 | T5 | 422 | T32 | 404 | ||||
others[2] | 34990 | 1 | T1 | 279 | T5 | 412 | T32 | 403 | ||||
others[3] | 58921 | 1 | T1 | 502 | T5 | 654 | T32 | 641 | ||||
false | 12720 | 1 | T1 | 50 | T2 | 176 | T5 | 50 | ||||
true | 23378 | 1 | T1 | 52 | T2 | 278 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 778 | 1 | T2 | 3 | T79 | 6 | T39 | 1 | ||||
others[1] | 721 | 1 | T2 | 6 | T7 | 1 | T79 | 5 | ||||
others[2] | 722 | 1 | T2 | 3 | T7 | 1 | T19 | 1 | ||||
others[3] | 1290 | 1 | T2 | 7 | T4 | 1 | T7 | 2 | ||||
false | 15059 | 1 | T1 | 2 | T2 | 161 | T3 | 1 | ||||
true | 4561 | 1 | T2 | 40 | T4 | 8 | T7 | 18 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |