Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	26634958	6610	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	26634958	276976	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	26634958	11130244	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	26634958	276978	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	26634958	6610	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	26634958	276976	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	26634958	11130244	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	26634958	276978	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	6610	0	0
T1	48609	23	0	0
T2	376836	103	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	19	0	0
T6	14984	0	0	0
T7	27770	12	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	10	0	0
T20	0	22	0	0
T32	0	19	0	0
T33	0	22	0	0
T42	0	3	0	0
T46	0	18	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	276976	0	0
T1	48609	1441	0	0
T2	376836	4043	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	639	0	0
T6	14984	0	0	0
T7	27770	272	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	553	0	0
T20	0	576	0	0
T32	0	1338	0	0
T33	0	1076	0	0
T42	0	247	0	0
T46	0	292	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	11130244	0	0
T1	48609	25492	0	0
T2	376836	183180	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	13026	0	0
T6	14984	0	0	0
T7	27770	10510	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T20	0	12141	0	0
T32	0	25935	0	0
T33	0	28525	0	0
T55	0	3357	0	0
T60	0	3147	0	0
T78	0	2549	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	276978	0	0
T1	48609	1444	0	0
T2	376836	4050	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	639	0	0
T6	14984	0	0	0
T7	27770	272	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	553	0	0
T20	0	576	0	0
T32	0	1338	0	0
T33	0	1076	0	0
T42	0	247	0	0
T46	0	292	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	6610	0	0
T1	48609	23	0	0
T2	376836	103	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	19	0	0
T6	14984	0	0	0
T7	27770	12	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	10	0	0
T20	0	22	0	0
T32	0	19	0	0
T33	0	22	0	0
T42	0	3	0	0
T46	0	18	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	276976	0	0
T1	48609	1441	0	0
T2	376836	4043	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	639	0	0
T6	14984	0	0	0
T7	27770	272	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	553	0	0
T20	0	576	0	0
T32	0	1338	0	0
T33	0	1076	0	0
T42	0	247	0	0
T46	0	292	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	11130244	0	0
T1	48609	25492	0	0
T2	376836	183180	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	13026	0	0
T6	14984	0	0	0
T7	27770	10510	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T20	0	12141	0	0
T32	0	25935	0	0
T33	0	28525	0	0
T55	0	3357	0	0
T60	0	3147	0	0
T78	0	2549	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	276978	0	0
T1	48609	1444	0	0
T2	376836	4050	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	639	0	0
T6	14984	0	0	0
T7	27770	272	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	553	0	0
T20	0	576	0	0
T32	0	1338	0	0
T33	0	1076	0	0
T42	0	247	0	0
T46	0	292	0	0