Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27242265	16498	0	0
intr_enable_rd_A	27242265	52268	0	0
reset_en_rd_A	27242265	2131	0	0
reset_en_regwen_rd_A	27242265	1919	0	0
wake_info_capture_dis_rd_A	27242265	1877	0	0
wakeup_en_rd_A	27242265	2931	0	0
wakeup_en_regwen_rd_A	27242265	1852	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	16498	0	0
T2	376836	13	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T17	0	26	0	0
T18	0	15	0	0
T19	1611	0	0	0
T51	0	33	0	0
T73	0	45	0	0
T81	0	7	0	0
T82	0	52	0	0
T97	0	8	0	0
T140	0	1	0	0
T141	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	52268	0	0
T2	376836	1492	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	258	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T20	0	68	0	0
T46	0	112	0	0
T101	0	16	0	0
T109	0	11	0	0
T142	0	197	0	0
T143	0	7	0	0
T144	0	15	0	0
T145	0	28	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	2131	0	0
T2	376836	2	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T85	0	8	0	0
T86	0	5	0	0
T141	0	6	0	0
T146	0	2	0	0
T147	0	16	0	0
T148	0	3	0	0
T149	0	4	0	0
T150	0	12	0	0
T151	0	6	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	1919	0	0
T2	376836	3	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T85	0	9	0	0
T141	0	5	0	0
T146	0	15	0	0
T147	0	7	0	0
T148	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	5	0	0
T153	0	12	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	1877	0	0
T2	376836	5	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T85	0	6	0	0
T141	0	8	0	0
T146	0	5	0	0
T147	0	1	0	0
T148	0	11	0	0
T149	0	1	0	0
T150	0	8	0	0
T152	0	7	0	0
T154	0	5	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	2931	0	0
T2	376836	8	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T81	0	2	0	0
T85	0	3	0	0
T141	0	6	0	0
T146	0	5	0	0
T147	0	7	0	0
T148	0	10	0	0
T149	0	8	0	0
T150	0	8	0	0
T152	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242265	1852	0	0
T2	376836	8	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	1611	0	0	0
T81	0	1	0	0
T85	0	5	0	0
T141	0	6	0	0
T146	0	4	0	0
T147	0	10	0	0
T148	0	6	0	0
T149	0	11	0	0
T150	0	2	0	0
T154	0	1	0	0