Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	79904874	158158	0	0
StatusRise_A	79904874	176451	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79904874	158158	0	0
T1	145827	207	0	0
T2	1130508	2345	0	0
T3	47169	3	0	0
T4	23238	54	0	0
T5	90453	219	0	0
T6	44952	3	0	0
T7	83310	257	0	0
T8	4113	0	0	0
T9	6732	3	0	0
T10	45999	3	0	0
T19	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79904874	176451	0	0
T1	145827	212	0	0
T2	1130508	2608	0	0
T3	47169	6	0	0
T4	23238	57	0	0
T5	90453	222	0	0
T6	44952	6	0	0
T7	83310	296	0	0
T8	4113	9	0	0
T9	6732	9	0	0
T10	45999	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26634958	58719	0	0
StatusRise_A	26634958	65336	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	58719	0	0
T1	48609	81	0	0
T2	376836	875	0	0
T3	15723	1	0	0
T4	7746	18	0	0
T5	30151	86	0	0
T6	14984	1	0	0
T7	27770	94	0	0
T8	1371	0	0	0
T9	2244	1	0	0
T10	15333	1	0	0
T19	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	65336	0	0
T1	48609	83	0	0
T2	376836	975	0	0
T3	15723	2	0	0
T4	7746	19	0	0
T5	30151	87	0	0
T6	14984	2	0	0
T7	27770	108	0	0
T8	1371	3	0	0
T9	2244	3	0	0
T10	15333	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26634958	58719	0	0
StatusRise_A	26634958	65336	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	58719	0	0
T1	48609	81	0	0
T2	376836	875	0	0
T3	15723	1	0	0
T4	7746	18	0	0
T5	30151	86	0	0
T6	14984	1	0	0
T7	27770	94	0	0
T8	1371	0	0	0
T9	2244	1	0	0
T10	15333	1	0	0
T19	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	65336	0	0
T1	48609	83	0	0
T2	376836	975	0	0
T3	15723	2	0	0
T4	7746	19	0	0
T5	30151	87	0	0
T6	14984	2	0	0
T7	27770	108	0	0
T8	1371	3	0	0
T9	2244	3	0	0
T10	15333	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26634958	40720	0	0
StatusRise_A	26634958	45779	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	40720	0	0
T1	48609	45	0	0
T2	376836	595	0	0
T3	15723	1	0	0
T4	7746	18	0	0
T5	30151	47	0	0
T6	14984	1	0	0
T7	27770	69	0	0
T8	1371	0	0	0
T9	2244	1	0	0
T10	15333	1	0	0
T19	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	45779	0	0
T1	48609	46	0	0
T2	376836	658	0	0
T3	15723	2	0	0
T4	7746	19	0	0
T5	30151	48	0	0
T6	14984	2	0	0
T7	27770	80	0	0
T8	1371	3	0	0
T9	2244	3	0	0
T10	15333	2	0	0