Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26635585	5217	0	0
EscTimeoutStoppedByClReset_A	26634958	3699606	0	0
EscTimeoutTriggersReset_A	5575560	337	0	0
RomAllowActiveState_A	26634958	64946	0	0
RomAllowCheckGoodState_A	26634958	64996	0	0
RomBlockActiveState_A	26634958	30225	0	0
RomBlockCheckGoodState_A	26634958	451663	0	0
RomIntgChkDisFalse_A	26634958	25859192	0	0
RomIntgChkDisTrue_A	26634958	206165	0	0
RstreqChkEsctimeout_A	26634958	5020	0	0
RstreqChkFsmterm_A	26634958	200	0	0
RstreqChkGlbesc_A	26634958	5020	0	0
RstreqChkMainpd_A	26634958	1057589	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26635585	5217	0	0
T3	15724	259	0	0
T4	7746	0	0	0
T5	30152	0	0	0
T6	14985	32	0	0
T7	27770	0	0	0
T8	1372	0	0	0
T9	2244	0	0	0
T10	15333	48	0	0
T19	1612	0	0	0
T55	11920	0	0	0
T100	0	28	0	0
T104	0	6	0	0
T135	0	94	0	0
T156	0	55	0	0
T157	0	60	0	0
T158	0	126	0	0
T159	0	106	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	3699606	0	0
T1	48609	9929	0	0
T2	376836	41128	0	0
T3	15723	43	0	0
T4	7746	369	0	0
T5	30151	6563	0	0
T6	14984	12	0	0
T7	27770	2164	0	0
T8	1371	25	0	0
T9	2244	40	0	0
T10	15333	25	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5575560	337	0	0
T3	203	3	0	0
T4	739	0	0	0
T5	6881	0	0	0
T6	675	2	0	0
T7	19789	0	0	0
T8	430	0	0	0
T9	191	2	0	0
T10	456	2	0	0
T19	533	0	0	0
T36	0	5	0	0
T55	1414	0	0	0
T100	0	3	0	0
T104	0	3	0	0
T107	0	7	0	0
T135	0	2	0	0
T160	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	64946	0	0
T1	48609	83	0	0
T2	376836	975	0	0
T3	15723	2	0	0
T4	7746	12	0	0
T5	30151	87	0	0
T6	14984	2	0	0
T7	27770	108	0	0
T8	1371	3	0	0
T9	2244	3	0	0
T10	15333	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	64996	0	0
T1	48609	83	0	0
T2	376836	975	0	0
T3	15723	2	0	0
T4	7746	13	0	0
T5	30151	87	0	0
T6	14984	2	0	0
T7	27770	108	0	0
T8	1371	3	0	0
T9	2244	3	0	0
T10	15333	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	30225	0	0
T19	1611	217	0	0
T32	57874	0	0	0
T33	54411	0	0	0
T34	4530	0	0	0
T35	2211	0	0	0
T36	648	0	0	0
T46	0	1	0	0
T47	0	92	0	0
T55	11919	0	0	0
T78	6354	0	0	0
T79	2353	0	0	0
T102	0	618	0	0
T160	736	0	0	0
T161	0	962	0	0
T162	0	1463	0	0
T163	0	1468	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	242	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	451663	0	0
T1	48609	3820	0	0
T2	376836	4040	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	2214	0	0
T6	14984	0	0	0
T7	27770	344	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T11	0	297	0	0
T19	0	24	0	0
T20	0	1346	0	0
T32	0	4054	0	0
T33	0	4084	0	0
T46	0	645	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	25859192	0	0
T1	48609	47028	0	0
T2	376836	369088	0	0
T3	15723	15654	0	0
T4	7746	6875	0	0
T5	30151	30097	0	0
T6	14984	14904	0	0
T7	27770	26701	0	0
T8	1371	1150	0	0
T9	2244	2130	0	0
T10	15333	15243	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	206165	0	0
T1	48609	1429	0	0
T2	376836	0	0	0
T3	15723	0	0	0
T4	7746	0	0	0
T5	30151	0	0	0
T6	14984	0	0	0
T7	27770	0	0	0
T8	1371	0	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	0	68	0	0
T20	0	259	0	0
T46	0	240	0	0
T47	0	62	0	0
T102	0	253	0	0
T161	0	328	0	0
T162	0	154	0	0
T163	0	1551	0	0
T167	0	915	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	5020	0	0
T2	376836	39	0	0
T3	15723	1	0	0
T4	7746	5	0	0
T5	30151	0	0	0
T6	14984	1	0	0
T7	27770	18	0	0
T8	1371	0	0	0
T9	2244	1	0	0
T10	15333	1	0	0
T19	1611	2	0	0
T34	0	9	0	0
T36	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	200	0	0
T14	40181	40	0	0
T15	0	40	0	0
T16	0	40	0	0
T21	0	40	0	0
T22	0	40	0	0
T23	53967	0	0	0
T24	6575	0	0	0
T25	15127	0	0	0
T26	839	0	0	0
T27	52983	0	0	0
T28	24044	0	0	0
T29	2100	0	0	0
T30	2477	0	0	0
T31	1853	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	5020	0	0
T2	376836	39	0	0
T3	15723	1	0	0
T4	7746	5	0	0
T5	30151	0	0	0
T6	14984	1	0	0
T7	27770	18	0	0
T8	1371	0	0	0
T9	2244	1	0	0
T10	15333	1	0	0
T19	1611	2	0	0
T34	0	9	0	0
T36	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26634958	1057589	0	0
T1	48609	6032	0	0
T2	376836	13739	0	0
T3	15723	0	0	0
T4	7746	275	0	0
T5	30151	2632	0	0
T6	14984	0	0	0
T7	27770	987	0	0
T8	1371	12	0	0
T9	2244	0	0	0
T10	15333	0	0	0
T19	0	82	0	0
T32	0	5196	0	0
T33	0	4100	0	0
T34	0	531	0	0