Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	535672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205626

1

T1

222

T3

1139

T4

66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	388411	1			T1	406		T2	1		T3	2215
values[0x0]	176170	1			T1	221		T3	1009		T4	56
values[0x1]	176717	1			T1	231		T3	1038		T4	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	424420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

316878

1

T1

349

T3

1748

T4

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2469	1			T17	2		T27	1		T14	6
valid_sources[0x01]	2425	1			T3	35		T4	3		T13	1
valid_sources[0x02]	3304	1			T4	5		T32	2		T13	1
valid_sources[0x03]	3434	1			T13	1		T27	5		T28	1
valid_sources[0x04]	2354	1			T3	5		T13	2		T27	2
valid_sources[0x05]	2401	1			T4	1		T13	1		T27	9
valid_sources[0x06]	2745	1			T32	2		T27	3		T28	1
valid_sources[0x07]	2322	1			T27	4		T14	4		T23	10
valid_sources[0x08]	2713	1			T32	1		T13	3		T27	9
valid_sources[0x09]	2643	1			T3	5		T4	1		T8	3
valid_sources[0x0a]	3489	1			T3	15		T13	1		T27	9
valid_sources[0x0b]	2601	1			T32	1		T27	1		T14	2
valid_sources[0x0c]	2807	1			T32	4		T27	1		T14	8
valid_sources[0x0d]	2245	1			T4	1		T13	2		T27	4
valid_sources[0x0e]	2254	1			T4	2		T13	1		T27	1
valid_sources[0x0f]	2757	1			T3	5		T4	5		T13	1
valid_sources[0x10]	2584	1			T27	5		T14	1		T24	3
valid_sources[0x11]	2635	1			T27	5		T14	7		T33	1
valid_sources[0x12]	2368	1			T4	2		T9	11		T32	3
valid_sources[0x13]	4190	1			T3	35		T4	2		T32	1
valid_sources[0x14]	2648	1			T4	1		T27	3		T14	5
valid_sources[0x15]	2411	1			T32	2		T13	2		T28	1
valid_sources[0x16]	2668	1			T13	1		T27	3		T14	9
valid_sources[0x17]	2328	1			T32	1		T13	6		T27	4
valid_sources[0x18]	2560	1			T27	11		T14	1		T11	1
valid_sources[0x19]	2828	1			T4	1		T32	1		T27	10
valid_sources[0x1a]	3570	1			T3	1217		T27	5		T14	1
valid_sources[0x1b]	2492	1			T4	1		T8	5		T13	1
valid_sources[0x1c]	2503	1			T17	1		T27	3		T14	10
valid_sources[0x1d]	2644	1			T13	1		T27	7		T14	1
valid_sources[0x1e]	3244	1			T13	1		T28	1		T14	4
valid_sources[0x1f]	2387	1			T9	6		T27	14		T14	5
valid_sources[0x20]	5565	1			T3	45		T13	1		T27	3
valid_sources[0x21]	2452	1			T13	1		T14	2		T33	3
valid_sources[0x22]	4255	1			T32	1		T28	1		T14	5
valid_sources[0x23]	3410	1			T32	3		T28	1		T14	4
valid_sources[0x24]	2541	1			T4	2		T32	3		T27	4
valid_sources[0x25]	5145	1			T27	10		T14	4		T23	10
valid_sources[0x26]	2566	1			T4	1		T14	2		T23	3
valid_sources[0x27]	3250	1			T13	2		T14	4		T33	1
valid_sources[0x28]	2642	1			T4	2		T27	2		T14	2
valid_sources[0x29]	3285	1			T13	1		T17	1		T14	7
valid_sources[0x2a]	3949	1			T3	14		T4	3		T32	6
valid_sources[0x2b]	2795	1			T4	3		T13	3		T28	1
valid_sources[0x2c]	2806	1			T3	5		T4	1		T8	2
valid_sources[0x2d]	3688	1			T4	1		T17	3		T33	1
valid_sources[0x2e]	3509	1			T27	8		T28	1		T14	1
valid_sources[0x2f]	2511	1			T4	2		T8	5		T27	5
valid_sources[0x30]	3618	1			T4	3		T13	2		T27	7
valid_sources[0x31]	2661	1			T4	1		T32	2		T13	1
valid_sources[0x32]	2433	1			T3	5		T8	2		T13	2
valid_sources[0x33]	4507	1			T1	7		T32	2		T27	2
valid_sources[0x34]	2661	1			T1	22		T28	1		T14	5
valid_sources[0x35]	2732	1			T4	1		T13	1		T27	1
valid_sources[0x36]	2468	1			T3	38		T4	1		T27	1
valid_sources[0x37]	4887	1			T3	26		T4	3		T8	4
valid_sources[0x38]	2655	1			T27	6		T23	15		T33	1
valid_sources[0x39]	3559	1			T4	1		T13	1		T27	2
valid_sources[0x3a]	2671	1			T13	2		T27	5		T14	11
valid_sources[0x3b]	2441	1			T4	1		T8	2		T27	4
valid_sources[0x3c]	2478	1			T7	3		T8	3		T32	3
valid_sources[0x3d]	2485	1			T4	1		T32	1		T13	2
valid_sources[0x3e]	2445	1			T1	20		T3	24		T13	4
valid_sources[0x3f]	2423	1			T14	5		T24	11		T83	1
valid_sources[0x40]	2573	1			T4	1		T32	2		T13	2
valid_sources[0x41]	2478	1			T4	1		T32	2		T13	1
valid_sources[0x42]	2973	1			T4	1		T32	2		T13	5
valid_sources[0x43]	2710	1			T4	2		T8	2		T32	1
valid_sources[0x44]	2660	1			T32	3		T13	1		T27	7
valid_sources[0x45]	3958	1			T3	14		T4	1		T32	1
valid_sources[0x46]	3599	1			T3	15		T4	1		T13	1
valid_sources[0x47]	5419	1			T32	1		T13	1		T14	2
valid_sources[0x48]	2514	1			T4	2		T7	16		T32	2
valid_sources[0x49]	2755	1			T13	2		T28	1		T14	2
valid_sources[0x4a]	2849	1			T3	5		T8	5		T32	1
valid_sources[0x4b]	2542	1			T4	2		T32	2		T13	2
valid_sources[0x4c]	2463	1			T32	5		T13	2		T27	3
valid_sources[0x4d]	2554	1			T13	1		T27	3		T14	6
valid_sources[0x4e]	2808	1			T27	1		T14	2		T24	12
valid_sources[0x4f]	4170	1			T4	3		T7	4		T13	2
valid_sources[0x50]	2897	1			T1	6		T4	3		T32	2
valid_sources[0x51]	2647	1			T13	1		T14	4		T33	1
valid_sources[0x52]	2654	1			T4	2		T27	1		T14	5
valid_sources[0x53]	2431	1			T13	1		T27	7		T14	6
valid_sources[0x54]	2552	1			T32	2		T13	1		T27	9
valid_sources[0x55]	3288	1			T4	4		T10	857		T14	2
valid_sources[0x56]	2491	1			T3	14		T32	1		T27	4
valid_sources[0x57]	2828	1			T27	1		T14	1		T83	1
valid_sources[0x58]	2439	1			T32	6		T27	7		T14	11
valid_sources[0x59]	2404	1			T4	4		T13	1		T27	6
valid_sources[0x5a]	2762	1			T3	15		T27	5		T14	3
valid_sources[0x5b]	2604	1			T3	15		T32	1		T27	3
valid_sources[0x5c]	3118	1			T16	1		T27	1		T28	2
valid_sources[0x5d]	6213	1			T4	2		T17	1		T14	1
valid_sources[0x5e]	2570	1			T4	2		T8	1		T32	1
valid_sources[0x5f]	3276	1			T8	1		T14	5		T24	2
valid_sources[0x60]	2736	1			T1	38		T4	1		T32	1
valid_sources[0x61]	2762	1			T27	3		T23	37		T24	3
valid_sources[0x62]	2716	1			T3	14		T8	3		T27	1
valid_sources[0x63]	3649	1			T27	6		T14	3		T23	1
valid_sources[0x64]	3502	1			T13	2		T28	1		T14	5
valid_sources[0x65]	2253	1			T4	1		T32	1		T27	1
valid_sources[0x66]	2541	1			T4	1		T32	2		T13	3
valid_sources[0x67]	2347	1			T4	2		T27	3		T23	4
valid_sources[0x68]	3300	1			T3	29		T4	3		T13	2
valid_sources[0x69]	3079	1			T8	4		T32	2		T27	2
valid_sources[0x6a]	2532	1			T13	3		T27	3		T28	2
valid_sources[0x6b]	2855	1			T4	2		T27	5		T14	6
valid_sources[0x6c]	6404	1			T3	5		T32	5		T27	7
valid_sources[0x6d]	2495	1			T3	15		T13	1		T28	1
valid_sources[0x6e]	2481	1			T13	1		T27	1		T14	4
valid_sources[0x6f]	2414	1			T4	5		T13	1		T27	7
valid_sources[0x70]	4066	1			T4	1		T13	1		T27	3
valid_sources[0x71]	2391	1			T4	4		T13	1		T27	1
valid_sources[0x72]	3403	1			T1	213		T32	2		T27	1
valid_sources[0x73]	2607	1			T4	1		T32	1		T14	11
valid_sources[0x74]	2613	1			T3	15		T27	1		T14	6
valid_sources[0x75]	2348	1			T4	1		T32	2		T27	4
valid_sources[0x76]	2483	1			T3	14		T4	1		T32	5
valid_sources[0x77]	2504	1			T8	5		T13	2		T27	5
valid_sources[0x78]	2773	1			T9	5		T13	2		T14	5
valid_sources[0x79]	2465	1			T13	1		T27	8		T28	1
valid_sources[0x7a]	3689	1			T27	1		T14	1		T23	15
valid_sources[0x7b]	2426	1			T32	2		T13	5		T27	1
valid_sources[0x7c]	2341	1			T13	1		T28	1		T14	4
valid_sources[0x7d]	2524	1			T4	1		T27	7		T24	6
valid_sources[0x7e]	3868	1			T27	17		T20	16		T175	1
valid_sources[0x7f]	2702	1			T13	5		T27	3		T28	1
valid_sources[0x80]	2806	1			T3	4		T4	3		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

104568

1

T1

103

T3

580

T4

24

values[0x0]

all_enables

biggest_size

65369

1

T1

92

T3

364

T4

23

values[0x1]

all_enables

biggest_size

35689

1

T1

27

T3

195

T4

19