SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34949 | 1 | T1 | 417 | T7 | 1 | T10 | 394 | ||||
others[1] | 34943 | 1 | T1 | 390 | T10 | 418 | T27 | 407 | ||||
others[2] | 35281 | 1 | T1 | 390 | T10 | 377 | T27 | 415 | ||||
others[3] | 58223 | 1 | T1 | 685 | T10 | 686 | T27 | 641 | ||||
false | 20774 | 1 | T1 | 50 | T3 | 150 | T7 | 3 | ||||
true | 31124 | 1 | T1 | 101 | T2 | 4 | T3 | 194 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34791 | 1 | T1 | 391 | T7 | 1 | T10 | 380 | ||||
others[1] | 35084 | 1 | T1 | 403 | T10 | 410 | T27 | 384 | ||||
others[2] | 35335 | 1 | T1 | 407 | T10 | 372 | T27 | 419 | ||||
others[3] | 58207 | 1 | T1 | 685 | T10 | 711 | T27 | 640 | ||||
false | 12975 | 1 | T1 | 50 | T3 | 75 | T7 | 4 | ||||
true | 23388 | 1 | T1 | 101 | T2 | 4 | T3 | 119 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 664 | 1 | T3 | 3 | T7 | 1 | T8 | 1 | ||||
others[1] | 679 | 1 | T3 | 4 | T8 | 1 | T32 | 2 | ||||
others[2] | 711 | 1 | T3 | 1 | T9 | 1 | T14 | 2 | ||||
others[3] | 1108 | 1 | T3 | 4 | T8 | 1 | T33 | 2 | ||||
false | 13808 | 1 | T1 | 1 | T2 | 4 | T3 | 85 | ||||
true | 3949 | 1 | T3 | 29 | T7 | 2 | T8 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |