Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25705741	17401	0	0
intr_enable_rd_A	25705741	49554	0	0
reset_en_rd_A	25705741	958	0	0
reset_en_regwen_rd_A	25705741	787	0	0
wake_info_capture_dis_rd_A	25705741	806	0	0
wakeup_en_rd_A	25705741	1791	0	0
wakeup_en_regwen_rd_A	25705741	859	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	17401	0	0
T3	220486	22	0	0
T4	4726	0	0	0
T5	877	0	0	0
T6	2108	0	0	0
T7	6046	0	0	0
T8	4638	0	0	0
T9	1995	0	0	0
T10	26273	0	0	0
T15	812	0	0	0
T20	0	68	0	0
T21	0	147	0	0
T32	8329	0	0	0
T39	0	140	0	0
T66	0	23	0	0
T67	0	55	0	0
T121	0	9	0	0
T122	0	37	0	0
T123	0	3	0	0
T124	0	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	49554	0	0
T9	1995	13	0	0
T10	26273	157	0	0
T13	2690	0	0	0
T15	812	0	0	0
T16	2488	0	0	0
T17	23473	0	0	0
T23	0	108	0	0
T27	19042	0	0	0
T28	2688	0	0	0
T29	1751	0	0	0
T32	8329	67	0	0
T33	0	44	0	0
T47	0	36	0	0
T63	0	11	0	0
T81	0	641	0	0
T85	0	9	0	0
T125	0	38	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	958	0	0
T78	0	1	0	0
T91	1430	0	0	0
T121	255967	4	0	0
T122	396894	0	0	0
T123	176503	0	0	0
T126	0	5	0	0
T127	0	6	0	0
T128	0	3	0	0
T129	0	19	0	0
T130	0	9	0	0
T131	0	9	0	0
T132	0	4	0	0
T133	0	11	0	0
T134	4192	0	0	0
T135	2048	0	0	0
T136	3195	0	0	0
T137	5380	0	0	0
T138	4222	0	0	0
T139	2049	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	787	0	0
T40	0	40	0	0
T78	0	3	0	0
T91	1430	0	0	0
T121	255967	5	0	0
T122	396894	0	0	0
T123	176503	0	0	0
T126	0	6	0	0
T127	0	12	0	0
T129	0	26	0	0
T130	0	6	0	0
T132	0	7	0	0
T133	0	2	0	0
T134	4192	0	0	0
T135	2048	0	0	0
T136	3195	0	0	0
T137	5380	0	0	0
T138	4222	0	0	0
T139	2049	0	0	0
T140	0	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	806	0	0
T78	0	6	0	0
T91	1430	0	0	0
T121	255967	1	0	0
T122	396894	0	0	0
T123	176503	0	0	0
T126	0	4	0	0
T127	0	3	0	0
T128	0	2	0	0
T129	0	17	0	0
T130	0	1	0	0
T131	0	8	0	0
T132	0	8	0	0
T134	4192	0	0	0
T135	2048	0	0	0
T136	3195	0	0	0
T137	5380	0	0	0
T138	4222	0	0	0
T139	2049	0	0	0
T140	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	1791	0	0
T78	0	3	0	0
T91	1430	0	0	0
T121	255967	2	0	0
T122	396894	0	0	0
T123	176503	0	0	0
T127	0	3	0	0
T129	0	19	0	0
T130	0	13	0	0
T131	0	8	0	0
T132	0	4	0	0
T133	0	6	0	0
T134	4192	0	0	0
T135	2048	0	0	0
T136	3195	0	0	0
T137	5380	0	0	0
T138	4222	0	0	0
T139	2049	0	0	0
T140	0	7	0	0
T141	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25705741	859	0	0
T78	0	3	0	0
T91	1430	0	0	0
T121	255967	5	0	0
T122	396894	0	0	0
T123	176503	0	0	0
T126	0	7	0	0
T127	0	12	0	0
T129	0	18	0	0
T130	0	8	0	0
T131	0	16	0	0
T132	0	1	0	0
T134	4192	0	0	0
T135	2048	0	0	0
T136	3195	0	0	0
T137	5380	0	0	0
T138	4222	0	0	0
T139	2049	0	0	0
T140	0	3	0	0
T142	0	16	0	0