Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	75395319	150999	0	0
StatusRise_A	75395319	168649	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75395319	150999	0	0
T1	101181	221	0	0
T2	5067	0	0	0
T3	661458	978	0	0
T4	14178	37	0	0
T5	2631	3	0	0
T6	6324	12	0	0
T7	18138	21	0	0
T8	13914	33	0	0
T9	5985	15	0	0
T10	78819	232	0	0
T32	0	72	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75395319	168649	0	0
T1	101181	224	0	0
T2	5067	12	0	0
T3	661458	1094	0	0
T4	14178	39	0	0
T5	2631	9	0	0
T6	6324	15	0	0
T7	18138	27	0	0
T8	13914	39	0	0
T9	5985	18	0	0
T10	78819	235	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25131773	56187	0	0
StatusRise_A	25131773	62579	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	56187	0	0
T1	33727	87	0	0
T2	1689	0	0	0
T3	220486	360	0	0
T4	4726	15	0	0
T5	877	1	0	0
T6	2108	4	0	0
T7	6046	7	0	0
T8	4638	11	0	0
T9	1995	5	0	0
T10	26273	90	0	0
T32	0	24	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	62579	0	0
T1	33727	88	0	0
T2	1689	4	0	0
T3	220486	403	0	0
T4	4726	16	0	0
T5	877	3	0	0
T6	2108	5	0	0
T7	6046	9	0	0
T8	4638	13	0	0
T9	1995	6	0	0
T10	26273	91	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25131773	56187	0	0
StatusRise_A	25131773	62579	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	56187	0	0
T1	33727	87	0	0
T2	1689	0	0	0
T3	220486	360	0	0
T4	4726	15	0	0
T5	877	1	0	0
T6	2108	4	0	0
T7	6046	7	0	0
T8	4638	11	0	0
T9	1995	5	0	0
T10	26273	90	0	0
T32	0	24	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	62579	0	0
T1	33727	88	0	0
T2	1689	4	0	0
T3	220486	403	0	0
T4	4726	16	0	0
T5	877	3	0	0
T6	2108	5	0	0
T7	6046	9	0	0
T8	4638	13	0	0
T9	1995	6	0	0
T10	26273	91	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25131773	38625	0	0
StatusRise_A	25131773	43491	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	38625	0	0
T1	33727	47	0	0
T2	1689	0	0	0
T3	220486	258	0	0
T4	4726	7	0	0
T5	877	1	0	0
T6	2108	4	0	0
T7	6046	7	0	0
T8	4638	11	0	0
T9	1995	5	0	0
T10	26273	52	0	0
T32	0	24	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	43491	0	0
T1	33727	48	0	0
T2	1689	4	0	0
T3	220486	288	0	0
T4	4726	7	0	0
T5	877	3	0	0
T6	2108	5	0	0
T7	6046	9	0	0
T8	4638	13	0	0
T9	1995	6	0	0
T10	26273	53	0	0