Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25132363	5790	0	0
EscTimeoutStoppedByClReset_A	25131773	3512733	0	0
EscTimeoutTriggersReset_A	5439255	344	0	0
RomAllowActiveState_A	25131773	62193	0	0
RomAllowCheckGoodState_A	25131773	62248	0	0
RomBlockActiveState_A	25131773	29881	0	0
RomBlockCheckGoodState_A	25131773	443368	0	0
RomIntgChkDisFalse_A	25131773	24391871	0	0
RomIntgChkDisTrue_A	25131773	193531	0	0
RstreqChkEsctimeout_A	25131773	4259	0	0
RstreqChkFsmterm_A	25131773	160	0	0
RstreqChkGlbesc_A	25131773	4259	0	0
RstreqChkMainpd_A	25131773	1011648	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25132363	5790	0	0
T11	14850	21	0	0
T12	793	0	0	0
T22	1583	0	0	0
T23	17597	0	0	0
T24	27710	0	0	0
T33	2353	0	0	0
T38	3228	0	0	0
T63	2059	0	0	0
T64	2099	0	0	0
T71	0	251	0	0
T72	0	32	0	0
T82	0	157	0	0
T143	0	19	0	0
T144	0	255	0	0
T145	0	255	0	0
T146	0	175	0	0
T147	0	55	0	0
T148	0	8	0	0
T149	945	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	3512733	0	0
T1	33727	4928	0	0
T2	1689	32	0	0
T3	220486	29772	0	0
T4	4726	822	0	0
T5	877	24	0	0
T6	2108	99	0	0
T7	6046	313	0	0
T8	4638	498	0	0
T9	1995	191	0	0
T10	26273	3592	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5439255	344	0	0
T5	264	5	0	0
T6	376	0	0	0
T7	468	0	0	0
T8	369	0	0	0
T9	253	0	0	0
T10	9361	0	0	0
T11	0	3	0	0
T12	0	4	0	0
T13	777	0	0	0
T15	553	0	0	0
T17	7844	0	0	0
T32	629	0	0	0
T71	0	3	0	0
T72	0	2	0	0
T76	0	2	0	0
T82	0	2	0	0
T143	0	2	0	0
T149	0	4	0	0
T150	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	62193	0	0
T1	33727	88	0	0
T2	1689	4	0	0
T3	220486	403	0	0
T4	4726	16	0	0
T5	877	3	0	0
T6	2108	5	0	0
T7	6046	9	0	0
T8	4638	13	0	0
T9	1995	6	0	0
T10	26273	91	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	62248	0	0
T1	33727	88	0	0
T2	1689	4	0	0
T3	220486	403	0	0
T4	4726	16	0	0
T5	877	3	0	0
T6	2108	5	0	0
T7	6046	9	0	0
T8	4638	13	0	0
T9	1995	6	0	0
T10	26273	91	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	29881	0	0
T7	6046	1210	0	0
T8	4638	0	0	0
T9	1995	0	0	0
T10	26273	0	0	0
T13	2690	0	0	0
T15	812	0	0	0
T16	2488	0	0	0
T17	23473	0	0	0
T23	0	5	0	0
T27	19042	12	0	0
T32	8329	0	0	0
T34	0	155	0	0
T151	0	488	0	0
T152	0	6	0	0
T153	0	149	0	0
T154	0	6	0	0
T155	0	151	0	0
T156	0	171	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	443368	0	0
T1	33727	2262	0	0
T2	1689	0	0	0
T3	220486	1722	0	0
T4	4726	0	0	0
T5	877	0	0	0
T6	2108	0	0	0
T7	6046	975	0	0
T8	4638	0	0	0
T9	1995	0	0	0
T10	26273	1336	0	0
T14	0	275	0	0
T23	0	823	0	0
T24	0	2211	0	0
T27	0	1329	0	0
T34	0	47	0	0
T125	0	322	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	24391871	0	0
T1	33727	33647	0	0
T2	1689	1351	0	0
T3	220486	217190	0	0
T4	4726	4672	0	0
T5	877	717	0	0
T6	2108	1716	0	0
T7	6046	3378	0	0
T8	4638	4457	0	0
T9	1995	1931	0	0
T10	26273	26179	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	193531	0	0
T7	6046	2527	0	0
T8	4638	0	0	0
T9	1995	0	0	0
T10	26273	0	0	0
T13	2690	0	0	0
T15	812	0	0	0
T16	2488	0	0	0
T17	23473	0	0	0
T23	0	441	0	0
T24	0	461	0	0
T27	19042	0	0	0
T32	8329	0	0	0
T151	0	1476	0	0
T152	0	382	0	0
T153	0	80	0	0
T154	0	272	0	0
T155	0	1018	0	0
T156	0	539	0	0
T157	0	499	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	4259	0	0
T3	220486	23	0	0
T4	4726	0	0	0
T5	877	1	0	0
T6	2108	0	0	0
T7	6046	4	0	0
T8	4638	5	0	0
T9	1995	2	0	0
T10	26273	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	7	0	0
T15	812	0	0	0
T17	0	20	0	0
T32	8329	10	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	160	0	0
T11	14850	0	0	0
T12	792	0	0	0
T14	52152	0	0	0
T16	2488	0	0	0
T17	23473	40	0	0
T18	0	40	0	0
T19	0	20	0	0
T25	0	40	0	0
T26	0	20	0	0
T27	19042	0	0	0
T28	2688	0	0	0
T29	1751	0	0	0
T30	1348	0	0	0
T31	2539	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	4259	0	0
T3	220486	23	0	0
T4	4726	0	0	0
T5	877	1	0	0
T6	2108	0	0	0
T7	6046	4	0	0
T8	4638	5	0	0
T9	1995	2	0	0
T10	26273	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	7	0	0
T15	812	0	0	0
T17	0	20	0	0
T32	8329	10	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25131773	1011648	0	0
T1	33727	3206	0	0
T2	1689	11	0	0
T3	220486	10948	0	0
T4	4726	0	0	0
T5	877	0	0	0
T6	2108	0	0	0
T7	6046	1373	0	0
T8	4638	526	0	0
T9	1995	197	0	0
T10	26273	1336	0	0
T15	0	17	0	0
T16	0	6	0	0
T32	0	1036	0	0