Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	498460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

189321

1

T1

21

T2

22

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	356643	1			T1	23		T2	45		T3	44
values[0x0]	164604	1			T1	8		T2	26		T3	8
values[0x1]	166534	1			T1	8		T2	22		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	394149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

293632

1

T1

24

T2

36

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2533	1			T10	4		T36	1		T14	23
valid_sources[0x01]	2230	1			T5	3		T9	1		T10	3
valid_sources[0x02]	3848	1			T10	5		T83	7		T14	34
valid_sources[0x03]	2233	1			T5	1		T10	7		T41	6
valid_sources[0x04]	2080	1			T3	1		T6	1		T10	2
valid_sources[0x05]	2427	1			T5	3		T9	1		T10	5
valid_sources[0x06]	4092	1			T9	2		T10	3		T36	1
valid_sources[0x07]	2472	1			T5	1		T10	1		T37	3
valid_sources[0x08]	3068	1			T10	9		T36	2		T37	1
valid_sources[0x09]	2661	1			T8	5		T10	3		T36	1
valid_sources[0x0a]	2108	1			T3	1		T5	1		T6	1
valid_sources[0x0b]	2503	1			T5	2		T6	3		T8	4
valid_sources[0x0c]	2612	1			T6	1		T10	3		T51	276
valid_sources[0x0d]	2536	1			T2	2		T5	5		T10	4
valid_sources[0x0e]	2566	1			T6	1		T10	2		T14	32
valid_sources[0x0f]	2359	1			T5	5		T6	1		T10	5
valid_sources[0x10]	2302	1			T10	4		T14	42		T16	14
valid_sources[0x11]	2311	1			T5	6		T6	1		T10	4
valid_sources[0x12]	2949	1			T2	3		T5	1		T8	15
valid_sources[0x13]	2629	1			T10	1		T24	3		T56	1
valid_sources[0x14]	2651	1			T10	4		T23	1		T36	2
valid_sources[0x15]	3043	1			T6	1		T10	1		T23	7
valid_sources[0x16]	4010	1			T5	1		T6	1		T9	3
valid_sources[0x17]	2141	1			T10	5		T37	2		T14	41
valid_sources[0x18]	2145	1			T3	1		T10	3		T83	1
valid_sources[0x19]	2650	1			T5	4		T6	1		T10	6
valid_sources[0x1a]	2176	1			T6	1		T10	2		T42	1
valid_sources[0x1b]	2362	1			T5	1		T10	3		T14	45
valid_sources[0x1c]	2675	1			T10	2		T36	2		T14	33
valid_sources[0x1d]	2253	1			T3	3		T6	1		T8	7
valid_sources[0x1e]	2309	1			T5	2		T10	5		T14	32
valid_sources[0x1f]	2199	1			T6	2		T9	1		T10	3
valid_sources[0x20]	3601	1			T5	7		T6	2		T8	3
valid_sources[0x21]	2305	1			T5	1		T6	1		T10	2
valid_sources[0x22]	3261	1			T10	3		T41	1		T37	3
valid_sources[0x23]	2347	1			T10	2		T37	1		T14	42
valid_sources[0x24]	3349	1			T9	1		T10	1		T83	15
valid_sources[0x25]	2379	1			T3	3		T5	3		T9	1
valid_sources[0x26]	3013	1			T9	1		T10	4		T14	37
valid_sources[0x27]	2478	1			T10	2		T83	6		T14	39
valid_sources[0x28]	2452	1			T10	3		T83	1		T38	1
valid_sources[0x29]	3440	1			T10	1		T24	1		T14	26
valid_sources[0x2a]	3407	1			T2	2		T8	7		T10	2
valid_sources[0x2b]	2359	1			T6	2		T10	8		T36	2
valid_sources[0x2c]	2139	1			T5	2		T9	1		T10	2
valid_sources[0x2d]	2504	1			T5	6		T6	1		T10	1
valid_sources[0x2e]	4329	1			T6	1		T10	1		T14	37
valid_sources[0x2f]	2115	1			T5	9		T10	1		T14	44
valid_sources[0x30]	3325	1			T5	2		T10	2		T83	2
valid_sources[0x31]	3207	1			T2	4		T5	3		T6	2
valid_sources[0x32]	2710	1			T6	1		T8	1		T9	1
valid_sources[0x33]	10553	1			T5	4		T10	6		T14	30
valid_sources[0x34]	3149	1			T10	4		T14	30		T16	30
valid_sources[0x35]	2360	1			T10	3		T83	6		T37	1
valid_sources[0x36]	2461	1			T5	4		T9	2		T10	2
valid_sources[0x37]	2727	1			T5	4		T10	4		T83	4
valid_sources[0x38]	2400	1			T8	18		T10	1		T41	1
valid_sources[0x39]	2264	1			T5	2		T8	1		T10	4
valid_sources[0x3a]	2322	1			T6	1		T10	8		T37	5
valid_sources[0x3b]	2123	1			T3	2		T6	2		T10	2
valid_sources[0x3c]	2857	1			T4	65		T10	5		T14	40
valid_sources[0x3d]	2584	1			T5	3		T6	1		T10	5
valid_sources[0x3e]	2938	1			T6	1		T10	6		T83	4
valid_sources[0x3f]	2230	1			T6	3		T10	8		T41	2
valid_sources[0x40]	3143	1			T24	2		T14	40		T60	1
valid_sources[0x41]	2204	1			T5	2		T6	1		T10	4
valid_sources[0x42]	2273	1			T10	2		T38	2		T14	43
valid_sources[0x43]	2464	1			T10	2		T83	3		T38	1
valid_sources[0x44]	2911	1			T5	2		T6	1		T10	2
valid_sources[0x45]	2232	1			T3	1		T6	2		T10	8
valid_sources[0x46]	3038	1			T2	4		T10	2		T14	43
valid_sources[0x47]	2537	1			T3	3		T9	1		T10	4
valid_sources[0x48]	2481	1			T9	2		T10	3		T37	2
valid_sources[0x49]	2364	1			T8	1		T10	5		T14	38
valid_sources[0x4a]	2204	1			T3	1		T6	1		T9	2
valid_sources[0x4b]	3356	1			T5	4		T6	1		T8	2
valid_sources[0x4c]	2981	1			T3	2		T5	5		T6	1
valid_sources[0x4d]	2160	1			T6	1		T10	5		T14	45
valid_sources[0x4e]	2467	1			T9	1		T10	4		T56	1
valid_sources[0x4f]	4733	1			T5	2		T6	1		T10	4
valid_sources[0x50]	2301	1			T5	1		T10	2		T36	1
valid_sources[0x51]	2412	1			T10	3		T38	2		T14	34
valid_sources[0x52]	2932	1			T5	1		T10	7		T14	43
valid_sources[0x53]	2613	1			T2	8		T5	8		T6	1
valid_sources[0x54]	3568	1			T10	2		T83	3		T14	33
valid_sources[0x55]	2035	1			T8	1		T9	1		T10	1
valid_sources[0x56]	2518	1			T10	6		T83	4		T14	39
valid_sources[0x57]	2362	1			T10	3		T37	1		T14	52
valid_sources[0x58]	3440	1			T10	3		T56	1		T38	2
valid_sources[0x59]	2159	1			T10	3		T14	29		T16	3
valid_sources[0x5a]	4347	1			T5	4		T9	1		T10	2
valid_sources[0x5b]	2527	1			T3	5		T10	2		T56	2
valid_sources[0x5c]	2261	1			T6	1		T9	1		T10	1
valid_sources[0x5d]	2638	1			T5	1		T10	3		T14	37
valid_sources[0x5e]	2591	1			T2	4		T6	1		T10	4
valid_sources[0x5f]	2728	1			T6	1		T10	4		T38	1
valid_sources[0x60]	4157	1			T6	4		T9	1		T10	1
valid_sources[0x61]	2055	1			T9	3		T10	1		T38	3
valid_sources[0x62]	2934	1			T6	1		T10	1		T14	43
valid_sources[0x63]	2420	1			T5	4		T6	2		T8	4
valid_sources[0x64]	2320	1			T5	1		T6	1		T10	3
valid_sources[0x65]	2110	1			T5	1		T10	3		T37	4
valid_sources[0x66]	2643	1			T6	2		T9	1		T10	3
valid_sources[0x67]	2128	1			T6	1		T10	7		T14	28
valid_sources[0x68]	2436	1			T2	28		T5	3		T10	5
valid_sources[0x69]	2343	1			T2	15		T10	4		T14	47
valid_sources[0x6a]	2345	1			T9	1		T10	2		T14	33
valid_sources[0x6b]	2595	1			T10	2		T14	33		T16	32
valid_sources[0x6c]	2439	1			T8	4		T9	1		T10	2
valid_sources[0x6d]	2230	1			T2	1		T6	2		T10	3
valid_sources[0x6e]	2047	1			T6	2		T10	6		T56	1
valid_sources[0x6f]	2172	1			T5	1		T10	5		T36	1
valid_sources[0x70]	3691	1			T3	4		T6	1		T10	2
valid_sources[0x71]	2482	1			T5	1		T6	1		T10	6
valid_sources[0x72]	2285	1			T10	3		T37	2		T38	1
valid_sources[0x73]	2339	1			T10	5		T83	8		T37	2
valid_sources[0x74]	2541	1			T6	4		T10	1		T36	1
valid_sources[0x75]	2360	1			T3	2		T6	1		T10	2
valid_sources[0x76]	2373	1			T5	1		T10	2		T24	1
valid_sources[0x77]	2486	1			T14	41		T60	1		T84	2
valid_sources[0x78]	5406	1			T9	1		T10	4		T14	37
valid_sources[0x79]	2256	1			T10	4		T83	6		T14	31
valid_sources[0x7a]	2464	1			T6	3		T10	1		T37	3
valid_sources[0x7b]	3299	1			T10	5		T83	4		T14	38
valid_sources[0x7c]	2256	1			T3	1		T5	1		T6	1
valid_sources[0x7d]	3384	1			T9	1		T10	7		T83	1
valid_sources[0x7e]	2353	1			T5	3		T6	2		T10	2
valid_sources[0x7f]	2426	1			T5	7		T6	1		T9	1
valid_sources[0x80]	2376	1			T3	3		T5	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

94012

1

T1

13

T2

9

T3

22

values[0x0]

all_enables

biggest_size

61475

1

T1

5

T2

10

T3

3

values[0x1]

all_enables

biggest_size

33834

1

T1

3

T2

3

T3

2