SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34857 | 1 | T4 | 1 | T10 | 309 | T104 | 411 | ||||
others[1] | 35105 | 1 | T10 | 305 | T24 | 1 | T38 | 1 | ||||
others[2] | 35227 | 1 | T10 | 307 | T162 | 1 | T104 | 380 | ||||
others[3] | 58518 | 1 | T9 | 1 | T10 | 490 | T38 | 1 | ||||
false | 19058 | 1 | T4 | 4 | T9 | 3 | T10 | 50 | ||||
true | 29081 | 1 | T1 | 5 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35063 | 1 | T4 | 1 | T10 | 329 | T38 | 1 | ||||
others[1] | 35151 | 1 | T10 | 308 | T104 | 392 | T175 | 396 | ||||
others[2] | 34823 | 1 | T10 | 292 | T36 | 1 | T162 | 1 | ||||
others[3] | 58365 | 1 | T4 | 1 | T9 | 1 | T10 | 483 | ||||
false | 12115 | 1 | T9 | 3 | T10 | 50 | T24 | 3 | ||||
true | 22188 | 1 | T1 | 5 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 689 | 1 | T5 | 9 | T23 | 2 | T14 | 9 | ||||
others[1] | 671 | 1 | T5 | 4 | T9 | 1 | T23 | 2 | ||||
others[2] | 673 | 1 | T5 | 4 | T23 | 2 | T38 | 1 | ||||
others[3] | 1104 | 1 | T5 | 11 | T14 | 7 | T16 | 3 | ||||
false | 13321 | 1 | T1 | 5 | T2 | 1 | T3 | 5 | ||||
true | 3801 | 1 | T4 | 4 | T8 | 7 | T9 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |