Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22246999	6215	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22246999	245425	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22246999	9216468	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22246999	245462	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22246999	6215	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22246999	245425	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22246999	9216468	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22246999	245462	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	6215	0	0
T1	1536	2	0	0
T2	5092	0	0	0
T3	3027	3	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	20	0	0
T14	0	79	0	0
T16	0	27	0	0
T22	0	38	0	0
T41	0	1	0	0
T80	0	11	0	0
T81	0	1	0	0
T82	0	27	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	245425	0	0
T1	1536	135	0	0
T2	5092	0	0	0
T3	3027	627	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	502	0	0
T14	0	2616	0	0
T16	0	828	0	0
T22	0	827	0	0
T41	0	14	0	0
T80	0	431	0	0
T81	0	10	0	0
T82	0	1008	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	9216468	0	0
T1	1536	121	0	0
T2	5092	1603	0	0
T3	3027	915	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	4152	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	11257	0	0
T14	0	162855	0	0
T41	0	934	0	0
T51	0	1086	0	0
T56	0	2058	0	0
T83	0	6388	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	245462	0	0
T1	1536	135	0	0
T2	5092	0	0	0
T3	3027	627	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	499	0	0
T14	0	2616	0	0
T16	0	828	0	0
T22	0	827	0	0
T41	0	14	0	0
T80	0	431	0	0
T81	0	10	0	0
T82	0	1008	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	6215	0	0
T1	1536	2	0	0
T2	5092	0	0	0
T3	3027	3	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	20	0	0
T14	0	79	0	0
T16	0	27	0	0
T22	0	38	0	0
T41	0	1	0	0
T80	0	11	0	0
T81	0	1	0	0
T82	0	27	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	245425	0	0
T1	1536	135	0	0
T2	5092	0	0	0
T3	3027	627	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	502	0	0
T14	0	2616	0	0
T16	0	828	0	0
T22	0	827	0	0
T41	0	14	0	0
T80	0	431	0	0
T81	0	10	0	0
T82	0	1008	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	9216468	0	0
T1	1536	121	0	0
T2	5092	1603	0	0
T3	3027	915	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	4152	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	11257	0	0
T14	0	162855	0	0
T41	0	934	0	0
T51	0	1086	0	0
T56	0	2058	0	0
T83	0	6388	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	245462	0	0
T1	1536	135	0	0
T2	5092	0	0	0
T3	3027	627	0	0
T4	1641	0	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	0	0	0
T10	24644	499	0	0
T14	0	2616	0	0
T16	0	828	0	0
T22	0	827	0	0
T41	0	14	0	0
T80	0	431	0	0
T81	0	10	0	0
T82	0	1008	0	0