Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22894446	15044	0	0
intr_enable_rd_A	22894446	28925	0	0
reset_en_rd_A	22894446	1006	0	0
reset_en_regwen_rd_A	22894446	913	0	0
wake_info_capture_dis_rd_A	22894446	941	0	0
wakeup_en_rd_A	22894446	2092	0	0
wakeup_en_regwen_rd_A	22894446	962	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	15044	0	0
T14	374508	14	0	0
T15	2454	0	0	0
T16	118092	7	0	0
T18	1656	0	0	0
T22	0	2	0	0
T39	1293	0	0	0
T45	0	26	0	0
T60	2559	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T87	0	19	0	0
T88	0	22	0	0
T105	0	19	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T142	0	16	0	0
T143	0	5	0	0
T144	0	63	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	28925	0	0
T10	24644	126	0	0
T15	0	55	0	0
T16	0	1037	0	0
T23	4980	0	0	0
T24	2131	25	0	0
T36	3418	11	0	0
T38	0	17	0	0
T40	715	0	0	0
T41	1239	5	0	0
T42	3494	0	0	0
T51	3550	0	0	0
T56	2448	6	0	0
T83	17714	61	0	0
T84	0	77	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	1006	0	0
T16	118092	4	0	0
T22	139790	0	0	0
T49	0	1	0	0
T57	0	18	0	0
T80	45543	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T86	16375	0	0	0
T88	0	6	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T113	6208	0	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	1	0	0
T150	0	3	0	0
T151	1521	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	913	0	0
T16	118092	7	0	0
T22	139790	0	0	0
T49	0	8	0	0
T57	0	77	0	0
T80	45543	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T86	16375	0	0	0
T88	0	9	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T113	6208	0	0	0
T146	0	11	0	0
T147	0	2	0	0
T148	0	10	0	0
T149	0	2	0	0
T150	0	9	0	0
T151	1521	0	0	0
T152	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	941	0	0
T16	118092	15	0	0
T22	139790	0	0	0
T49	0	5	0	0
T57	0	48	0	0
T80	45543	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T86	16375	0	0	0
T88	0	6	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T113	6208	0	0	0
T146	0	10	0	0
T147	0	5	0	0
T148	0	4	0	0
T149	0	8	0	0
T150	0	6	0	0
T151	1521	0	0	0
T152	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	2092	0	0
T16	118092	14	0	0
T22	139790	0	0	0
T49	0	2	0	0
T57	0	59	0	0
T80	45543	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T86	16375	0	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T113	6208	0	0	0
T123	0	7	0	0
T135	0	9	0	0
T146	0	8	0	0
T147	0	7	0	0
T148	0	3	0	0
T150	0	6	0	0
T151	1521	0	0	0
T152	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894446	962	0	0
T16	118092	13	0	0
T22	139790	0	0	0
T49	0	6	0	0
T57	0	39	0	0
T80	45543	0	0	0
T84	15789	0	0	0
T85	6040	0	0	0
T86	16375	0	0	0
T111	1212	0	0	0
T112	3252	0	0	0
T113	6208	0	0	0
T123	0	10	0	0
T135	0	28	0	0
T146	0	7	0	0
T148	0	10	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	1521	0	0	0
T152	0	4	0	0