Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66740997	140812	0	0
StatusRise_A	66740997	157558	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66740997	140812	0	0
T1	4608	12	0	0
T2	15276	18	0	0
T3	9081	12	0	0
T4	4923	18	0	0
T5	14334	0	0	0
T6	31194	27	0	0
T7	4845	0	0	0
T8	8463	54	0	0
T9	5814	18	0	0
T10	73932	209	0	0
T23	0	54	0	0
T41	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66740997	157558	0	0
T1	4608	15	0	0
T2	15276	21	0	0
T3	9081	15	0	0
T4	4923	21	0	0
T5	14334	3	0	0
T6	31194	30	0	0
T7	4845	12	0	0
T8	8463	60	0	0
T9	5814	21	0	0
T10	73932	215	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22246999	52394	0	0
StatusRise_A	22246999	58425	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	52394	0	0
T1	1536	4	0	0
T2	5092	7	0	0
T3	3027	4	0	0
T4	1641	6	0	0
T5	4778	0	0	0
T6	10398	11	0	0
T7	1615	0	0	0
T8	2821	18	0	0
T9	1938	6	0	0
T10	24644	86	0	0
T23	0	18	0	0
T41	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	58425	0	0
T1	1536	5	0	0
T2	5092	8	0	0
T3	3027	5	0	0
T4	1641	7	0	0
T5	4778	1	0	0
T6	10398	12	0	0
T7	1615	4	0	0
T8	2821	20	0	0
T9	1938	7	0	0
T10	24644	88	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22246999	52395	0	0
StatusRise_A	22246999	58425	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	52395	0	0
T1	1536	4	0	0
T2	5092	7	0	0
T3	3027	4	0	0
T4	1641	6	0	0
T5	4778	0	0	0
T6	10398	11	0	0
T7	1615	0	0	0
T8	2821	18	0	0
T9	1938	6	0	0
T10	24644	86	0	0
T23	0	18	0	0
T41	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	58425	0	0
T1	1536	5	0	0
T2	5092	8	0	0
T3	3027	5	0	0
T4	1641	7	0	0
T5	4778	1	0	0
T6	10398	12	0	0
T7	1615	4	0	0
T8	2821	20	0	0
T9	1938	7	0	0
T10	24644	88	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22246999	36023	0	0
StatusRise_A	22246999	40708	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	36023	0	0
T1	1536	4	0	0
T2	5092	4	0	0
T3	3027	4	0	0
T4	1641	6	0	0
T5	4778	0	0	0
T6	10398	5	0	0
T7	1615	0	0	0
T8	2821	18	0	0
T9	1938	6	0	0
T10	24644	37	0	0
T23	0	18	0	0
T41	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	40708	0	0
T1	1536	5	0	0
T2	5092	5	0	0
T3	3027	5	0	0
T4	1641	7	0	0
T5	4778	1	0	0
T6	10398	6	0	0
T7	1615	4	0	0
T8	2821	20	0	0
T9	1938	7	0	0
T10	24644	39	0	0