Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	22247594	5652	0	0
EscTimeoutStoppedByClReset_A	22246999	3077230	0	0
EscTimeoutTriggersReset_A	5086975	319	0	0
RomAllowActiveState_A	22246999	58053	0	0
RomAllowCheckGoodState_A	22246999	58103	0	0
RomBlockActiveState_A	22246999	26129	0	0
RomBlockCheckGoodState_A	22246999	432056	0	0
RomIntgChkDisFalse_A	22246999	21583364	0	0
RomIntgChkDisTrue_A	22246999	143551	0	0
RstreqChkEsctimeout_A	22246999	4236	0	0
RstreqChkFsmterm_A	22246999	180	0	0
RstreqChkGlbesc_A	22246999	4236	0	0
RstreqChkMainpd_A	22246999	896568	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22247594	5652	0	0
T11	1385	22	0	0
T12	833	0	0	0
T13	0	55	0	0
T29	0	30	0	0
T32	0	145	0	0
T44	1553	0	0	0
T45	316819	0	0	0
T95	0	33	0	0
T102	1456	0	0	0
T114	71503	0	0	0
T153	0	268	0	0
T154	0	15	0	0
T155	0	30	0	0
T156	0	145	0	0
T157	0	17	0	0
T158	5417	0	0	0
T159	1916	0	0	0
T160	3539	0	0	0
T161	4891	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	3077230	0	0
T1	1536	104	0	0
T2	5092	855	0	0
T3	3027	48	0	0
T4	1641	142	0	0
T5	4778	32	0	0
T6	10398	2140	0	0
T7	1615	2	0	0
T8	2821	302	0	0
T9	1938	101	0	0
T10	24644	3609	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5086975	319	0	0
T11	232	3	0	0
T12	266	4	0	0
T13	0	3	0	0
T29	0	3	0	0
T32	0	3	0	0
T44	854	0	0	0
T45	117215	0	0	0
T95	0	3	0	0
T102	245	0	0	0
T114	25182	0	0	0
T153	0	3	0	0
T154	0	4	0	0
T155	0	2	0	0
T156	0	3	0	0
T158	792	0	0	0
T159	516	0	0	0
T160	2591	0	0	0
T161	1845	0	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	58053	0	0
T1	1536	5	0	0
T2	5092	8	0	0
T3	3027	5	0	0
T4	1641	7	0	0
T5	4778	1	0	0
T6	10398	12	0	0
T7	1615	4	0	0
T8	2821	13	0	0
T9	1938	7	0	0
T10	24644	88	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	58103	0	0
T1	1536	5	0	0
T2	5092	8	0	0
T3	3027	5	0	0
T4	1641	7	0	0
T5	4778	1	0	0
T6	10398	12	0	0
T7	1615	4	0	0
T8	2821	14	0	0
T9	1938	7	0	0
T10	24644	88	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	26129	0	0
T4	1641	200	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	298	0	0
T10	24644	0	0	0
T23	4980	0	0	0
T24	0	150	0	0
T36	0	674	0	0
T38	0	205	0	0
T40	715	0	0	0
T41	1239	0	0	0
T159	0	297	0	0
T162	0	241	0	0
T163	0	3	0	0
T164	0	334	0	0
T165	0	601	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	432056	0	0
T4	1641	70	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	119	0	0
T10	24644	1324	0	0
T14	0	3511	0	0
T16	0	1306	0	0
T22	0	1628	0	0
T23	4980	0	0	0
T24	0	48	0	0
T36	0	268	0	0
T38	0	34	0	0
T40	715	0	0	0
T41	1239	0	0	0
T80	0	527	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	21583364	0	0
T1	1536	1191	0	0
T2	5092	5014	0	0
T3	3027	2659	0	0
T4	1641	943	0	0
T5	4778	4713	0	0
T6	10398	10329	0	0
T7	1615	1262	0	0
T8	2821	1865	0	0
T9	1938	850	0	0
T10	24644	23997	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	143551	0	0
T4	1641	619	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	0	0	0
T9	1938	1020	0	0
T10	24644	467	0	0
T23	4980	0	0	0
T24	0	1046	0	0
T36	0	321	0	0
T38	0	93	0	0
T40	715	0	0	0
T41	1239	0	0	0
T159	0	247	0	0
T162	0	1025	0	0
T164	0	1241	0	0
T166	0	1485	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	4236	0	0
T4	1641	3	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	11	0	0
T9	1938	4	0	0
T10	24644	0	0	0
T14	0	78	0	0
T23	4980	5	0	0
T24	0	4	0	0
T36	0	3	0	0
T37	0	9	0	0
T38	0	4	0	0
T40	715	0	0	0
T41	1239	0	0	0
T42	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	180	0	0
T19	19439	40	0	0
T20	0	40	0	0
T21	0	40	0	0
T25	0	20	0	0
T26	0	40	0	0
T27	14083	0	0	0
T28	5034	0	0	0
T29	2003	0	0	0
T30	1032	0	0	0
T31	16846	0	0	0
T32	15452	0	0	0
T33	6919	0	0	0
T34	3529	0	0	0
T35	2573	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	4236	0	0
T4	1641	3	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	0	0	0
T8	2821	11	0	0
T9	1938	4	0	0
T10	24644	0	0	0
T14	0	78	0	0
T23	4980	5	0	0
T24	0	4	0	0
T36	0	3	0	0
T37	0	9	0	0
T38	0	4	0	0
T40	715	0	0	0
T41	1239	0	0	0
T42	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22246999	896568	0	0
T4	1641	150	0	0
T5	4778	0	0	0
T6	10398	0	0	0
T7	1615	17	0	0
T8	2821	75	0	0
T9	1938	154	0	0
T10	24644	1293	0	0
T23	4980	112	0	0
T24	0	51	0	0
T36	0	411	0	0
T37	0	425	0	0
T40	715	5	0	0
T41	1239	0	0	0