Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12014 |
1 |
|
|
T2 |
4 |
|
T4 |
23 |
|
T5 |
23 |
auto[1] |
14715 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
27 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12621 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
24 |
auto[1] |
14108 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T4 |
26 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1630 |
1 |
|
|
T6 |
7 |
|
T55 |
2 |
|
T80 |
3 |
auto[0] |
auto[0] |
auto[1] |
1678 |
1 |
|
|
T6 |
4 |
|
T55 |
1 |
|
T80 |
4 |
auto[0] |
auto[1] |
auto[0] |
4465 |
1 |
|
|
T2 |
1 |
|
T4 |
12 |
|
T5 |
14 |
auto[0] |
auto[1] |
auto[1] |
4241 |
1 |
|
|
T2 |
3 |
|
T4 |
11 |
|
T5 |
9 |
auto[1] |
auto[0] |
auto[0] |
1617 |
1 |
|
|
T6 |
4 |
|
T55 |
2 |
|
T80 |
1 |
auto[1] |
auto[0] |
auto[1] |
2247 |
1 |
|
|
T2 |
3 |
|
T6 |
6 |
|
T55 |
2 |
auto[1] |
auto[1] |
auto[0] |
4909 |
1 |
|
|
T1 |
1 |
|
T4 |
12 |
|
T5 |
14 |
auto[1] |
auto[1] |
auto[1] |
5942 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T4 |
15 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11871 |
1 |
|
|
T2 |
4 |
|
T4 |
17 |
|
T5 |
25 |
auto[1] |
14858 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
33 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12616 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T4 |
21 |
auto[1] |
14113 |
1 |
|
|
T2 |
6 |
|
T4 |
29 |
|
T5 |
28 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1637 |
1 |
|
|
T6 |
5 |
|
T55 |
1 |
|
T80 |
2 |
auto[0] |
auto[0] |
auto[1] |
1619 |
1 |
|
|
T6 |
4 |
|
T55 |
2 |
|
T80 |
2 |
auto[0] |
auto[1] |
auto[0] |
4466 |
1 |
|
|
T2 |
3 |
|
T4 |
7 |
|
T5 |
11 |
auto[0] |
auto[1] |
auto[1] |
4149 |
1 |
|
|
T2 |
1 |
|
T4 |
10 |
|
T5 |
14 |
auto[1] |
auto[0] |
auto[0] |
1691 |
1 |
|
|
T2 |
1 |
|
T6 |
6 |
|
T55 |
1 |
auto[1] |
auto[0] |
auto[1] |
2225 |
1 |
|
|
T2 |
2 |
|
T6 |
6 |
|
T55 |
3 |
auto[1] |
auto[1] |
auto[0] |
4822 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T4 |
14 |
auto[1] |
auto[1] |
auto[1] |
6120 |
1 |
|
|
T2 |
3 |
|
T4 |
19 |
|
T5 |
14 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11948 |
1 |
|
|
T2 |
4 |
|
T4 |
20 |
|
T5 |
22 |
auto[1] |
14781 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
30 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12677 |
1 |
|
|
T2 |
5 |
|
T4 |
27 |
|
T5 |
23 |
auto[1] |
14052 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T4 |
23 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1593 |
1 |
|
|
T2 |
1 |
|
T6 |
4 |
|
T55 |
3 |
auto[0] |
auto[0] |
auto[1] |
1670 |
1 |
|
|
T2 |
1 |
|
T6 |
4 |
|
T80 |
6 |
auto[0] |
auto[1] |
auto[0] |
4539 |
1 |
|
|
T2 |
1 |
|
T4 |
10 |
|
T5 |
11 |
auto[0] |
auto[1] |
auto[1] |
4146 |
1 |
|
|
T2 |
1 |
|
T4 |
10 |
|
T5 |
11 |
auto[1] |
auto[0] |
auto[0] |
1678 |
1 |
|
|
T6 |
7 |
|
T55 |
3 |
|
T80 |
3 |
auto[1] |
auto[0] |
auto[1] |
2231 |
1 |
|
|
T2 |
1 |
|
T6 |
6 |
|
T55 |
1 |
auto[1] |
auto[1] |
auto[0] |
4867 |
1 |
|
|
T2 |
3 |
|
T4 |
17 |
|
T5 |
12 |
auto[1] |
auto[1] |
auto[1] |
6005 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T4 |
13 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12058 |
1 |
|
|
T2 |
1 |
|
T4 |
25 |
|
T5 |
24 |
auto[1] |
14671 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T4 |
25 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12521 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T4 |
28 |
auto[1] |
14208 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T4 |
22 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1594 |
1 |
|
|
T6 |
6 |
|
T55 |
1 |
|
T80 |
4 |
auto[0] |
auto[0] |
auto[1] |
1708 |
1 |
|
|
T6 |
6 |
|
T55 |
2 |
|
T80 |
3 |
auto[0] |
auto[1] |
auto[0] |
4480 |
1 |
|
|
T4 |
16 |
|
T5 |
15 |
|
T6 |
7 |
auto[0] |
auto[1] |
auto[1] |
4276 |
1 |
|
|
T2 |
1 |
|
T4 |
9 |
|
T5 |
9 |
auto[1] |
auto[0] |
auto[0] |
1688 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T55 |
1 |
auto[1] |
auto[0] |
auto[1] |
2182 |
1 |
|
|
T2 |
1 |
|
T6 |
8 |
|
T55 |
3 |
auto[1] |
auto[1] |
auto[0] |
4759 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T4 |
12 |
auto[1] |
auto[1] |
auto[1] |
6042 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
13 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12039 |
1 |
|
|
T2 |
4 |
|
T4 |
12 |
|
T5 |
19 |
auto[1] |
14690 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
38 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12630 |
1 |
|
|
T2 |
4 |
|
T4 |
27 |
|
T5 |
24 |
auto[1] |
14099 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
23 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1642 |
1 |
|
|
T2 |
1 |
|
T6 |
5 |
|
T55 |
4 |
auto[0] |
auto[0] |
auto[1] |
1761 |
1 |
|
|
T6 |
3 |
|
T55 |
1 |
|
T80 |
3 |
auto[0] |
auto[1] |
auto[0] |
4476 |
1 |
|
|
T4 |
7 |
|
T5 |
8 |
|
T6 |
8 |
auto[0] |
auto[1] |
auto[1] |
4160 |
1 |
|
|
T2 |
3 |
|
T4 |
5 |
|
T5 |
11 |
auto[1] |
auto[0] |
auto[0] |
1572 |
1 |
|
|
T6 |
5 |
|
T55 |
1 |
|
T80 |
3 |
auto[1] |
auto[0] |
auto[1] |
2197 |
1 |
|
|
T2 |
2 |
|
T6 |
8 |
|
T55 |
1 |
auto[1] |
auto[1] |
auto[0] |
4940 |
1 |
|
|
T2 |
3 |
|
T4 |
20 |
|
T5 |
16 |
auto[1] |
auto[1] |
auto[1] |
5981 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
18 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7172 |
1 |
|
|
T2 |
3 |
|
T6 |
21 |
|
T55 |
7 |
auto[1] |
19557 |
1 |
|
|
T1 |
2 |
|
T2 |
8 |
|
T4 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12146 |
1 |
|
|
T2 |
4 |
|
T4 |
29 |
|
T5 |
26 |
auto[1] |
14583 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
21 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12711 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T4 |
25 |
auto[1] |
14018 |
1 |
|
|
T2 |
4 |
|
T4 |
25 |
|
T5 |
26 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1661 |
1 |
|
|
T2 |
2 |
|
T6 |
5 |
|
T55 |
3 |
auto[0] |
auto[0] |
auto[1] |
1650 |
1 |
|
|
T6 |
4 |
|
T55 |
1 |
|
T80 |
5 |
auto[0] |
auto[1] |
auto[0] |
4656 |
1 |
|
|
T2 |
2 |
|
T4 |
16 |
|
T5 |
12 |
auto[0] |
auto[1] |
auto[1] |
4179 |
1 |
|
|
T4 |
13 |
|
T5 |
14 |
|
T6 |
10 |
auto[1] |
auto[0] |
auto[0] |
1629 |
1 |
|
|
T6 |
5 |
|
T55 |
3 |
|
T80 |
2 |
auto[1] |
auto[0] |
auto[1] |
2232 |
1 |
|
|
T2 |
1 |
|
T6 |
7 |
|
T80 |
5 |
auto[1] |
auto[1] |
auto[0] |
4765 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T4 |
9 |
auto[1] |
auto[1] |
auto[1] |
5957 |
1 |
|
|
T2 |
3 |
|
T4 |
12 |
|
T5 |
12 |