Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	514382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199516

1

T1

471

T2

282

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	377000	1			T1	788		T2	574		T3	1
values[0x0]	168383	1			T1	203		T2	126		T4	211
values[0x1]	168515	1			T1	227		T2	145		T4	241

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	407823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

306075

1

T1

648

T2

407

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2761	1			T2	3		T4	2		T5	1
valid_sources[0x01]	2671	1			T2	4		T5	8		T6	11
valid_sources[0x02]	3534	1			T2	1		T4	7		T5	3
valid_sources[0x03]	2512	1			T2	2		T4	4		T5	1
valid_sources[0x04]	3250	1			T2	9		T4	2		T5	6
valid_sources[0x05]	3032	1			T2	3		T4	4		T5	7
valid_sources[0x06]	2592	1			T2	1		T4	3		T6	14
valid_sources[0x07]	2200	1			T2	8		T5	1		T6	15
valid_sources[0x08]	2627	1			T1	5		T2	2		T4	4
valid_sources[0x09]	3675	1			T4	4		T5	9		T6	17
valid_sources[0x0a]	2181	1			T2	2		T5	2		T6	15
valid_sources[0x0b]	2659	1			T1	126		T4	3		T6	16
valid_sources[0x0c]	2223	1			T2	2		T4	1		T5	15
valid_sources[0x0d]	3378	1			T2	8		T4	6		T5	6
valid_sources[0x0e]	2703	1			T2	3		T4	3		T5	5
valid_sources[0x0f]	2599	1			T2	1		T5	6		T6	11
valid_sources[0x10]	2322	1			T2	7		T5	4		T6	9
valid_sources[0x11]	2300	1			T1	2		T2	8		T4	6
valid_sources[0x12]	3889	1			T2	8		T4	3		T5	1
valid_sources[0x13]	3457	1			T2	9		T4	4		T5	3
valid_sources[0x14]	2490	1			T4	3		T5	4		T6	13
valid_sources[0x15]	3279	1			T2	6		T5	4		T6	13
valid_sources[0x16]	2405	1			T2	3		T4	2		T6	18
valid_sources[0x17]	2563	1			T2	1		T4	1		T6	6
valid_sources[0x18]	2424	1			T2	3		T4	2		T5	1
valid_sources[0x19]	2348	1			T2	2		T4	4		T5	5
valid_sources[0x1a]	2686	1			T2	4		T4	4		T5	2
valid_sources[0x1b]	2557	1			T2	3		T4	3		T5	12
valid_sources[0x1c]	3971	1			T2	4		T4	4		T5	7
valid_sources[0x1d]	2544	1			T2	3		T4	2		T5	1
valid_sources[0x1e]	2654	1			T2	9		T4	10		T6	11
valid_sources[0x1f]	3305	1			T2	1		T4	3		T5	4
valid_sources[0x20]	2587	1			T2	3		T4	2		T5	19
valid_sources[0x21]	2195	1			T2	1		T4	4		T5	4
valid_sources[0x22]	2596	1			T1	5		T2	3		T4	4
valid_sources[0x23]	2792	1			T2	1		T4	13		T5	2
valid_sources[0x24]	2505	1			T2	1		T4	4		T6	15
valid_sources[0x25]	2325	1			T2	3		T4	2		T5	3
valid_sources[0x26]	2425	1			T2	5		T4	3		T5	4
valid_sources[0x27]	2671	1			T2	1		T4	7		T6	13
valid_sources[0x28]	3766	1			T2	1		T4	1		T5	8
valid_sources[0x29]	3036	1			T2	4		T4	2		T5	1
valid_sources[0x2a]	3776	1			T2	3		T4	2		T5	1
valid_sources[0x2b]	2451	1			T2	2		T4	4		T5	9
valid_sources[0x2c]	3387	1			T2	1		T4	8		T5	13
valid_sources[0x2d]	3055	1			T1	10		T2	3		T4	3
valid_sources[0x2e]	2540	1			T2	1		T4	1		T6	13
valid_sources[0x2f]	2468	1			T4	4		T5	2		T6	13
valid_sources[0x30]	2273	1			T2	2		T4	4		T6	10
valid_sources[0x31]	3185	1			T1	5		T2	2		T4	4
valid_sources[0x32]	2573	1			T1	79		T4	8		T6	18
valid_sources[0x33]	2348	1			T2	1		T4	4		T6	12
valid_sources[0x34]	2581	1			T2	6		T4	1		T5	4
valid_sources[0x35]	2991	1			T2	7		T4	1		T6	11
valid_sources[0x36]	3438	1			T2	1		T4	7		T5	6
valid_sources[0x37]	2712	1			T2	1		T4	3		T5	1
valid_sources[0x38]	3258	1			T2	4		T4	3		T5	7
valid_sources[0x39]	2352	1			T1	5		T2	4		T4	19
valid_sources[0x3a]	2326	1			T4	1		T5	2		T6	9
valid_sources[0x3b]	2641	1			T1	2		T2	5		T4	5
valid_sources[0x3c]	2459	1			T2	4		T4	7		T6	12
valid_sources[0x3d]	2135	1			T2	1		T4	6		T6	11
valid_sources[0x3e]	2889	1			T2	6		T4	2		T5	2
valid_sources[0x3f]	3021	1			T1	69		T2	1		T4	4
valid_sources[0x40]	2496	1			T2	3		T4	3		T5	4
valid_sources[0x41]	2319	1			T2	3		T4	6		T5	2
valid_sources[0x42]	2683	1			T2	4		T4	3		T5	7
valid_sources[0x43]	2256	1			T2	3		T4	1		T5	16
valid_sources[0x44]	2819	1			T2	4		T4	3		T6	13
valid_sources[0x45]	2742	1			T2	9		T4	5		T6	12
valid_sources[0x46]	3999	1			T2	5		T4	2		T5	12
valid_sources[0x47]	2699	1			T2	6		T4	9		T5	8
valid_sources[0x48]	3368	1			T4	1		T6	13		T8	1
valid_sources[0x49]	2616	1			T2	1		T4	2		T6	9
valid_sources[0x4a]	3544	1			T1	13		T2	2		T4	8
valid_sources[0x4b]	2488	1			T2	5		T4	5		T5	9
valid_sources[0x4c]	3334	1			T2	3		T4	2		T6	18
valid_sources[0x4d]	2226	1			T2	3		T4	3		T5	8
valid_sources[0x4e]	2254	1			T1	11		T2	6		T4	4
valid_sources[0x4f]	2419	1			T2	4		T4	2		T5	2
valid_sources[0x50]	2454	1			T2	3		T4	2		T5	1
valid_sources[0x51]	2398	1			T2	7		T4	3		T5	4
valid_sources[0x52]	2318	1			T1	5		T2	2		T4	2
valid_sources[0x53]	2580	1			T2	4		T4	2		T6	10
valid_sources[0x54]	2547	1			T2	2		T5	3		T6	16
valid_sources[0x55]	2815	1			T2	5		T4	6		T6	16
valid_sources[0x56]	2409	1			T2	2		T4	3		T5	3
valid_sources[0x57]	2462	1			T1	5		T2	2		T4	2
valid_sources[0x58]	2278	1			T2	2		T4	1		T5	1
valid_sources[0x59]	2772	1			T2	3		T4	4		T6	15
valid_sources[0x5a]	2809	1			T2	1		T4	1		T5	1
valid_sources[0x5b]	2468	1			T1	20		T2	2		T5	4
valid_sources[0x5c]	3241	1			T2	5		T5	14		T6	9
valid_sources[0x5d]	3039	1			T2	2		T4	1		T5	1
valid_sources[0x5e]	2419	1			T2	3		T4	3		T5	3
valid_sources[0x5f]	2433	1			T2	5		T5	5		T6	5
valid_sources[0x60]	3715	1			T2	5		T4	7		T5	2
valid_sources[0x61]	2687	1			T2	1		T4	1		T6	17
valid_sources[0x62]	3931	1			T2	2		T4	3		T5	9
valid_sources[0x63]	2395	1			T2	3		T4	4		T5	1
valid_sources[0x64]	3092	1			T4	5		T5	3		T6	11
valid_sources[0x65]	2258	1			T1	5		T2	2		T4	1
valid_sources[0x66]	2193	1			T2	7		T4	3		T6	13
valid_sources[0x67]	3277	1			T2	1		T4	1		T5	12
valid_sources[0x68]	4907	1			T2	9		T4	3		T5	3
valid_sources[0x69]	2257	1			T2	3		T4	2		T6	13
valid_sources[0x6a]	3054	1			T1	10		T2	7		T4	11
valid_sources[0x6b]	2340	1			T2	7		T4	6		T5	3
valid_sources[0x6c]	3274	1			T4	4		T5	7		T6	14
valid_sources[0x6d]	2680	1			T2	5		T4	2		T5	20
valid_sources[0x6e]	2526	1			T1	6		T4	2		T5	4
valid_sources[0x6f]	2492	1			T2	5		T4	3		T6	11
valid_sources[0x70]	2489	1			T2	6		T4	2		T5	16
valid_sources[0x71]	2296	1			T2	6		T4	2		T5	2
valid_sources[0x72]	2391	1			T2	4		T4	6		T5	5
valid_sources[0x73]	2241	1			T2	5		T4	7		T5	3
valid_sources[0x74]	2812	1			T1	84		T2	3		T4	2
valid_sources[0x75]	3918	1			T2	3		T4	5		T5	4
valid_sources[0x76]	2350	1			T2	2		T4	3		T6	16
valid_sources[0x77]	2422	1			T2	3		T4	4		T5	11
valid_sources[0x78]	2519	1			T2	4		T4	2		T6	12
valid_sources[0x79]	2277	1			T2	1		T5	5		T6	15
valid_sources[0x7a]	2396	1			T2	1		T4	5		T5	2
valid_sources[0x7b]	3401	1			T2	5		T4	4		T5	1
valid_sources[0x7c]	2373	1			T2	2		T4	7		T6	14
valid_sources[0x7d]	2576	1			T2	1		T4	3		T5	5
valid_sources[0x7e]	3458	1			T2	3		T4	4		T5	2
valid_sources[0x7f]	2296	1			T2	2		T4	4		T6	16
valid_sources[0x80]	3041	1			T2	5		T4	8		T6	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103213

1

T1

282

T2

212

T3

1

values[0x0]

all_enables

biggest_size

62340

1

T1

108

T2

45

T4

82

values[0x1]

all_enables

biggest_size

33963

1

T1

81

T2

25

T4

37