SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34818 | 1 | T4 | 407 | T5 | 399 | T7 | 399 | ||||
others[1] | 34819 | 1 | T4 | 389 | T5 | 401 | T7 | 411 | ||||
others[2] | 34640 | 1 | T4 | 395 | T5 | 393 | T7 | 375 | ||||
others[3] | 57697 | 1 | T4 | 673 | T5 | 683 | T7 | 683 | ||||
false | 18299 | 1 | T2 | 6 | T4 | 50 | T5 | 50 | ||||
true | 28344 | 1 | T1 | 12 | T2 | 15 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34542 | 1 | T4 | 427 | T5 | 393 | T7 | 390 | ||||
others[1] | 34880 | 1 | T4 | 373 | T5 | 391 | T7 | 418 | ||||
others[2] | 34568 | 1 | T4 | 413 | T5 | 400 | T7 | 357 | ||||
others[3] | 57962 | 1 | T4 | 659 | T5 | 678 | T7 | 703 | ||||
false | 11729 | 1 | T2 | 3 | T4 | 50 | T5 | 50 | ||||
true | 21845 | 1 | T1 | 12 | T2 | 12 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 665 | 1 | T1 | 3 | T2 | 2 | T6 | 4 | ||||
others[1] | 697 | 1 | T1 | 1 | T2 | 2 | T6 | 1 | ||||
others[2] | 675 | 1 | T1 | 3 | T2 | 1 | T6 | 2 | ||||
others[3] | 1077 | 1 | T1 | 3 | T2 | 2 | T6 | 2 | ||||
false | 13635 | 1 | T1 | 37 | T2 | 25 | T3 | 4 | ||||
true | 4078 | 1 | T1 | 15 | T2 | 9 | T6 | 38 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |