Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24877633	15476	0	0
intr_enable_rd_A	24877633	34391	0	0
reset_en_rd_A	24877633	2377	0	0
reset_en_regwen_rd_A	24877633	2111	0	0
wake_info_capture_dis_rd_A	24877633	2120	0	0
wakeup_en_rd_A	24877633	3596	0	0
wakeup_en_regwen_rd_A	24877633	2156	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	15476	0	0
T1	23931	77	0	0
T2	22523	0	0	0
T3	1010	0	0	0
T4	30438	0	0	0
T5	18091	0	0	0
T6	91725	0	0	0
T7	13686	0	0	0
T8	2993	0	0	0
T9	7166	0	0	0
T10	1205	0	0	0
T19	0	12	0	0
T20	0	4	0	0
T34	0	19	0	0
T58	0	10	0	0
T73	0	19	0	0
T83	0	22	0	0
T122	0	11	0	0
T123	0	36	0	0
T124	0	42	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	34391	0	0
T4	30438	81	0	0
T5	18091	0	0	0
T6	91725	0	0	0
T7	13686	0	0	0
T8	2993	0	0	0
T9	7166	0	0	0
T10	1205	0	0	0
T11	15757	0	0	0
T20	0	1134	0	0
T21	0	18	0	0
T22	0	13	0	0
T35	8182	34	0	0
T36	0	60	0	0
T39	0	1	0	0
T55	13733	0	0	0
T60	0	23	0	0
T125	0	2	0	0
T126	0	105	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	2377	0	0
T34	393366	4	0	0
T49	0	134	0	0
T53	0	10	0	0
T76	0	8	0	0
T88	0	11	0	0
T127	0	8	0	0
T128	0	12	0	0
T129	0	9	0	0
T130	0	5	0	0
T131	0	1	0	0
T132	2393	0	0	0
T133	8343	0	0	0
T134	2716	0	0	0
T135	2225	0	0	0
T136	1013	0	0	0
T137	1427	0	0	0
T138	2912	0	0	0
T139	11034	0	0	0
T140	1635	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	2111	0	0
T20	137839	3	0	0
T34	0	8	0	0
T53	0	2	0	0
T59	6923	0	0	0
T60	8691	0	0	0
T61	5553	0	0	0
T76	0	9	0	0
T88	0	16	0	0
T122	196249	0	0	0
T127	0	9	0	0
T128	0	8	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	10	0	0
T141	1374	0	0	0
T142	2547	0	0	0
T143	19134	0	0	0
T144	1630	0	0	0
T145	5758	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	2120	0	0
T20	137839	9	0	0
T34	0	6	0	0
T52	0	1	0	0
T53	0	9	0	0
T59	6923	0	0	0
T60	8691	0	0	0
T61	5553	0	0	0
T88	0	11	0	0
T122	196249	0	0	0
T127	0	5	0	0
T128	0	8	0	0
T129	0	3	0	0
T130	0	4	0	0
T141	1374	0	0	0
T142	2547	0	0	0
T143	19134	0	0	0
T144	1630	0	0	0
T145	5758	0	0	0
T146	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	3596	0	0
T20	137839	2	0	0
T34	0	15	0	0
T52	0	5	0	0
T53	0	2	0	0
T59	6923	0	0	0
T60	8691	0	0	0
T61	5553	0	0	0
T88	0	4	0	0
T122	196249	0	0	0
T127	0	3	0	0
T128	0	4	0	0
T129	0	6	0	0
T130	0	10	0	0
T141	1374	0	0	0
T142	2547	0	0	0
T143	19134	0	0	0
T144	1630	0	0	0
T145	5758	0	0	0
T146	0	7	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877633	2156	0	0
T20	137839	1	0	0
T34	0	15	0	0
T49	0	67	0	0
T52	0	9	0	0
T53	0	9	0	0
T59	6923	0	0	0
T60	8691	0	0	0
T61	5553	0	0	0
T76	0	4	0	0
T88	0	13	0	0
T122	196249	0	0	0
T127	0	4	0	0
T128	0	9	0	0
T131	0	21	0	0
T141	1374	0	0	0
T142	2547	0	0	0
T143	19134	0	0	0
T144	1630	0	0	0
T145	5758	0	0	0