Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72718077	144696	0	0
StatusRise_A	72718077	161541	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72718077	144696	0	0
T1	71793	185	0	0
T2	67569	167	0	0
T3	3030	0	0	0
T4	91314	201	0	0
T5	54273	216	0	0
T6	275175	632	0	0
T7	41058	206	0	0
T8	8979	12	0	0
T9	21498	67	0	0
T10	3615	0	0	0
T35	0	43	0	0
T55	0	45	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72718077	161541	0	0
T1	71793	220	0	0
T2	67569	193	0	0
T3	3030	12	0	0
T4	91314	204	0	0
T5	54273	222	0	0
T6	275175	689	0	0
T7	41058	209	0	0
T8	8979	15	0	0
T9	21498	72	0	0
T10	3615	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24239359	53633	0	0
StatusRise_A	24239359	59722	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	53633	0	0
T1	23931	63	0	0
T2	22523	58	0	0
T3	1010	0	0	0
T4	30438	81	0	0
T5	18091	85	0	0
T6	91725	223	0	0
T7	13686	83	0	0
T8	2993	4	0	0
T9	7166	27	0	0
T10	1205	0	0	0
T35	0	16	0	0
T55	0	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	59722	0	0
T1	23931	75	0	0
T2	22523	67	0	0
T3	1010	4	0	0
T4	30438	82	0	0
T5	18091	87	0	0
T6	91725	245	0	0
T7	13686	84	0	0
T8	2993	5	0	0
T9	7166	29	0	0
T10	1205	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24239359	53633	0	0
StatusRise_A	24239359	59723	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	53633	0	0
T1	23931	63	0	0
T2	22523	58	0	0
T3	1010	0	0	0
T4	30438	81	0	0
T5	18091	85	0	0
T6	91725	223	0	0
T7	13686	83	0	0
T8	2993	4	0	0
T9	7166	27	0	0
T10	1205	0	0	0
T35	0	16	0	0
T55	0	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	59723	0	0
T1	23931	75	0	0
T2	22523	67	0	0
T3	1010	4	0	0
T4	30438	82	0	0
T5	18091	87	0	0
T6	91725	245	0	0
T7	13686	84	0	0
T8	2993	5	0	0
T9	7166	29	0	0
T10	1205	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24239359	37430	0	0
StatusRise_A	24239359	42096	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	37430	0	0
T1	23931	59	0	0
T2	22523	51	0	0
T3	1010	0	0	0
T4	30438	39	0	0
T5	18091	46	0	0
T6	91725	186	0	0
T7	13686	40	0	0
T8	2993	4	0	0
T9	7166	13	0	0
T10	1205	0	0	0
T35	0	11	0	0
T55	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	42096	0	0
T1	23931	70	0	0
T2	22523	59	0	0
T3	1010	4	0	0
T4	30438	40	0	0
T5	18091	48	0	0
T6	91725	199	0	0
T7	13686	41	0	0
T8	2993	5	0	0
T9	7166	14	0	0
T10	1205	6	0	0