Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24239956	6424	0	0
EscTimeoutStoppedByClReset_A	24239359	3442487	0	0
EscTimeoutTriggersReset_A	4717177	314	0	0
RomAllowActiveState_A	24239359	59338	0	0
RomAllowCheckGoodState_A	24239359	59388	0	0
RomBlockActiveState_A	24239359	27865	0	0
RomBlockCheckGoodState_A	24239359	409520	0	0
RomIntgChkDisFalse_A	24239359	23596796	0	0
RomIntgChkDisTrue_A	24239359	116536	0	0
RstreqChkEsctimeout_A	24239359	4315	0	0
RstreqChkFsmterm_A	24239359	160	0	0
RstreqChkGlbesc_A	24239359	4315	0	0
RstreqChkMainpd_A	24239359	944552	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239956	6424	0	0
T11	15758	117	0	0
T13	0	30	0	0
T21	1413	0	0	0
T36	6056	0	0	0
T40	1052	0	0	0
T44	2737	0	0	0
T45	3126	0	0	0
T80	6654	0	0	0
T132	0	40	0	0
T148	0	31	0	0
T149	0	218	0	0
T150	0	144	0	0
T151	0	45	0	0
T152	0	9	0	0
T153	0	119	0	0
T154	0	29	0	0
T155	3256	0	0	0
T156	1652	0	0	0
T157	739	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	3442487	0	0
T1	23931	1594	0	0
T2	22523	2929	0	0
T3	1010	1	0	0
T4	30438	5059	0	0
T5	18091	3206	0	0
T6	91725	16066	0	0
T7	13686	2808	0	0
T8	2993	96	0	0
T9	7166	890	0	0
T10	1205	45	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4717177	314	0	0
T11	193	2	0	0
T12	0	5	0	0
T13	0	2	0	0
T21	1996	0	0	0
T36	3153	0	0	0
T40	305	0	0	0
T44	266	0	0	0
T45	296	0	0	0
T80	2586	0	0	0
T148	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0
T155	929	0	0	0
T156	561	0	0	0
T157	232	0	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	6	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	59338	0	0
T1	23931	75	0	0
T2	22523	67	0	0
T3	1010	4	0	0
T4	30438	82	0	0
T5	18091	87	0	0
T6	91725	245	0	0
T7	13686	84	0	0
T8	2993	5	0	0
T9	7166	29	0	0
T10	1205	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	59388	0	0
T1	23931	75	0	0
T2	22523	67	0	0
T3	1010	4	0	0
T4	30438	82	0	0
T5	18091	87	0	0
T6	91725	245	0	0
T7	13686	84	0	0
T8	2993	5	0	0
T9	7166	29	0	0
T10	1205	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	27865	0	0
T7	13686	12	0	0
T8	2993	0	0	0
T9	7166	0	0	0
T10	1205	0	0	0
T11	15757	0	0	0
T22	0	196	0	0
T35	8182	0	0	0
T37	0	492	0	0
T39	0	214	0	0
T40	1051	0	0	0
T44	2736	0	0	0
T45	3125	0	0	0
T55	13733	0	0	0
T141	0	68	0	0
T143	0	4	0	0
T145	0	1218	0	0
T162	0	1509	0	0
T163	0	1	0	0
T164	0	421	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	409520	0	0
T2	22523	69	0	0
T3	1010	0	0	0
T4	30438	1805	0	0
T5	18091	1346	0	0
T6	91725	367	0	0
T7	13686	943	0	0
T8	2993	0	0	0
T9	7166	367	0	0
T10	1205	0	0	0
T22	0	130	0	0
T35	0	253	0	0
T36	0	297	0	0
T55	13733	0	0	0
T165	0	136	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	23596796	0	0
T1	23931	23226	0	0
T2	22523	21863	0	0
T3	1010	661	0	0
T4	30438	30384	0	0
T5	18091	17913	0	0
T6	91725	90280	0	0
T7	13686	13618	0	0
T8	2993	2652	0	0
T9	7166	7002	0	0
T10	1205	785	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	116536	0	0
T14	1856	0	0	0
T21	1412	843	0	0
T22	0	321	0	0
T23	0	418	0	0
T37	0	1361	0	0
T39	0	1067	0	0
T41	1842	0	0	0
T80	6653	0	0	0
T81	1055	0	0	0
T125	1771	0	0	0
T141	0	112	0	0
T143	0	226	0	0
T145	0	286	0	0
T157	738	0	0	0
T162	0	621	0	0
T163	0	719	0	0
T165	4598	0	0	0
T166	2006	0	0	0
T167	6254	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	4315	0	0
T1	23931	15	0	0
T2	22523	9	0	0
T3	1010	0	0	0
T4	30438	0	0	0
T5	18091	0	0	0
T6	91725	27	0	0
T7	13686	0	0	0
T8	2993	0	0	0
T9	7166	0	0	0
T10	1205	0	0	0
T11	0	1	0	0
T21	0	3	0	0
T22	0	2	0	0
T40	0	1	0	0
T41	0	5	0	0
T42	0	2	0	0
T43	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	160	0	0
T16	14782	40	0	0
T17	0	20	0	0
T18	0	20	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	2227	0	0	0
T27	895	0	0	0
T28	17233	0	0	0
T29	1609	0	0	0
T30	11723	0	0	0
T31	3194	0	0	0
T32	3184	0	0	0
T33	3372	0	0	0
T34	393366	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	4315	0	0
T1	23931	15	0	0
T2	22523	9	0	0
T3	1010	0	0	0
T4	30438	0	0	0
T5	18091	0	0	0
T6	91725	27	0	0
T7	13686	0	0	0
T8	2993	0	0	0
T9	7166	0	0	0
T10	1205	0	0	0
T11	0	1	0	0
T21	0	3	0	0
T22	0	2	0	0
T40	0	1	0	0
T41	0	5	0	0
T42	0	2	0	0
T43	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24239359	944552	0	0
T1	23931	1331	0	0
T2	22523	1301	0	0
T3	1010	12	0	0
T4	30438	1763	0	0
T5	18091	2132	0	0
T6	91725	5336	0	0
T7	13686	574	0	0
T8	2993	0	0	0
T9	7166	497	0	0
T10	1205	20	0	0
T35	0	203	0	0