Group : pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
WakeupAonTimer_ctrl_cg 100.00 1 100 1 64 64
WakeupDbgCable_ctrl_cg 100.00 1 100 1 64 64
WakeupPin_ctrl_cg 100.00 1 100 1 64 64
WakeupSensorCtrl_ctrl_cg 100.00 1 100 1 64 64
WakeupSysrst_ctrl_cg 100.00 1 100 1 64 64
WakeupUsb_ctrl_cg 100.00 1 100 1 64 64




Group Instance : WakeupAonTimer_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupAonTimer_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupAonTimer_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupAonTimer_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupDbgCable_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupDbgCable_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupDbgCable_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupDbgCable_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupPin_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupPin_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupPin_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupPin_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupSensorCtrl_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupSensorCtrl_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupSensorCtrl_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupSensorCtrl_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupSysrst_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupSysrst_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupSysrst_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupSysrst_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupUsb_ctrl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupUsb_ctrl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupUsb_ctrl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
capture_cp 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupUsb_ctrl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
wakeup_cross 8 0 8 100.00 100 1 1 0


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11620 1 T3 3 T6 1 T8 1
auto[1] 14104 1 T3 6 T9 1 T14 27



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12150 1 T3 6 T14 21 T26 28
auto[1] 13574 1 T3 3 T6 1 T8 1



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1568 1 T3 1 T54 3 T55 3
auto[0] auto[0] auto[1] 1633 1 T54 1 T55 3 T78 1
auto[0] auto[1] auto[0] 4332 1 T3 2 T14 11 T26 14
auto[0] auto[1] auto[1] 4087 1 T6 1 T8 1 T14 12
auto[1] auto[0] auto[0] 1591 1 T3 1 T55 3 T78 1
auto[1] auto[0] auto[1] 2145 1 T3 2 T54 1 T55 6
auto[1] auto[1] auto[0] 4659 1 T3 2 T14 10 T26 14
auto[1] auto[1] auto[1] 5709 1 T3 1 T9 1 T14 17


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11705 1 T3 6 T6 1 T8 1
auto[1] 14019 1 T3 3 T9 1 T14 35



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12202 1 T3 4 T6 1 T9 1
auto[1] 13522 1 T3 5 T8 1 T14 24



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1611 1 T3 1 T55 4 T78 2
auto[0] auto[0] auto[1] 1635 1 T3 2 T54 2 T55 5
auto[0] auto[1] auto[0] 4401 1 T3 2 T6 1 T14 7
auto[0] auto[1] auto[1] 4058 1 T3 1 T8 1 T14 8
auto[1] auto[0] auto[0] 1597 1 T54 2 T55 4 T60 1
auto[1] auto[0] auto[1] 2094 1 T3 1 T54 1 T55 2
auto[1] auto[1] auto[0] 4593 1 T3 1 T9 1 T14 19
auto[1] auto[1] auto[1] 5735 1 T3 1 T14 16 T26 13


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11462 1 T3 6 T6 1 T8 1
auto[1] 14262 1 T3 3 T9 1 T14 27



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12151 1 T3 4 T6 1 T14 19
auto[1] 13573 1 T3 5 T8 1 T9 1



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1551 1 T54 1 T55 3 T78 1
auto[0] auto[0] auto[1] 1552 1 T3 3 T55 4 T78 2
auto[0] auto[1] auto[0] 4296 1 T3 3 T6 1 T14 9
auto[0] auto[1] auto[1] 4063 1 T8 1 T14 14 T26 12
auto[1] auto[0] auto[0] 1618 1 T54 2 T55 3 T78 1
auto[1] auto[0] auto[1] 2216 1 T3 1 T54 2 T55 5
auto[1] auto[1] auto[0] 4686 1 T3 1 T14 10 T26 10
auto[1] auto[1] auto[1] 5742 1 T3 1 T9 1 T14 17


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11711 1 T3 5 T6 1 T8 1
auto[1] 14013 1 T3 4 T9 1 T14 24



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12126 1 T3 4 T6 1 T8 1
auto[1] 13598 1 T3 5 T9 1 T14 23



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1571 1 T3 1 T55 3 T78 2
auto[0] auto[0] auto[1] 1635 1 T3 1 T54 2 T55 4
auto[0] auto[1] auto[0] 4399 1 T6 1 T8 1 T14 14
auto[0] auto[1] auto[1] 4106 1 T3 3 T14 12 T26 14
auto[1] auto[0] auto[0] 1566 1 T3 1 T54 1 T55 4
auto[1] auto[0] auto[1] 2165 1 T3 1 T54 2 T55 4
auto[1] auto[1] auto[0] 4590 1 T3 2 T14 13 T26 7
auto[1] auto[1] auto[1] 5692 1 T9 1 T14 11 T26 12


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11668 1 T3 2 T6 1 T8 1
auto[1] 14056 1 T3 7 T9 1 T14 27



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12285 1 T3 5 T6 1 T8 1
auto[1] 13439 1 T3 4 T14 24 T26 28



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1609 1 T78 2 T60 1 T16 19
auto[0] auto[0] auto[1] 1655 1 T3 2 T54 2 T55 5
auto[0] auto[1] auto[0] 4394 1 T6 1 T8 1 T14 14
auto[0] auto[1] auto[1] 4010 1 T14 9 T26 13 T44 1
auto[1] auto[0] auto[0] 1568 1 T3 1 T54 3 T55 5
auto[1] auto[0] auto[1] 2105 1 T3 1 T55 5 T78 2
auto[1] auto[1] auto[0] 4714 1 T3 4 T9 1 T14 12
auto[1] auto[1] auto[1] 5669 1 T3 1 T14 15 T26 15


Summary for Variable capture_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for capture_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6937 1 T3 4 T54 5 T55 15
auto[1] 18787 1 T3 5 T6 1 T8 1



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11543 1 T3 5 T6 1 T8 1
auto[1] 14181 1 T3 4 T9 1 T14 27



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12039 1 T3 2 T6 1 T8 1
auto[1] 13685 1 T3 7 T14 28 T26 31



Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for wakeup_cross

Bins
enable_cpcapture_cpwakeup_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1560 1 T3 1 T55 6 T78 3
auto[0] auto[0] auto[1] 1627 1 T3 2 T54 1 T55 3
auto[0] auto[1] auto[0] 4349 1 T6 1 T8 1 T14 11
auto[0] auto[1] auto[1] 4007 1 T3 2 T14 12 T26 20
auto[1] auto[0] auto[0] 1517 1 T55 3 T16 17 T24 14
auto[1] auto[0] auto[1] 2233 1 T3 1 T54 4 T55 3
auto[1] auto[1] auto[0] 4613 1 T3 1 T9 1 T14 11
auto[1] auto[1] auto[1] 5818 1 T3 2 T14 16 T26 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%