Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	483372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

178956

1

T1

49

T3

39

T5

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	340316	1			T1	92		T2	1		T3	55
values[0x0]	160799	1			T1	15		T3	27		T5	12
values[0x1]	161213	1			T1	18		T3	39		T5	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	382589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

279739

1

T1

62

T3

61

T5

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2006	1			T1	1		T14	4		T26	2
valid_sources[0x01]	2118	1			T1	1		T9	1		T14	1
valid_sources[0x02]	4303	1			T7	2		T14	10		T15	2
valid_sources[0x03]	2246	1			T14	1		T26	6		T54	1
valid_sources[0x04]	2446	1			T1	2		T3	3		T7	1
valid_sources[0x05]	3084	1			T1	1		T14	4		T26	2
valid_sources[0x06]	3912	1			T1	1		T7	1		T26	6
valid_sources[0x07]	2033	1			T14	4		T15	1		T26	5
valid_sources[0x08]	1889	1			T26	2		T143	4		T76	2
valid_sources[0x09]	2263	1			T14	1		T26	4		T44	1
valid_sources[0x0a]	1980	1			T14	3		T26	5		T54	1
valid_sources[0x0b]	1901	1			T1	2		T26	6		T54	1
valid_sources[0x0c]	1918	1			T1	1		T14	1		T26	3
valid_sources[0x0d]	3274	1			T7	1		T14	3		T26	3
valid_sources[0x0e]	2079	1			T14	5		T26	1		T143	3
valid_sources[0x0f]	4079	1			T1	1		T3	8		T14	1
valid_sources[0x10]	2255	1			T1	1		T7	1		T14	11
valid_sources[0x11]	2367	1			T14	3		T15	4		T26	4
valid_sources[0x12]	2073	1			T7	1		T14	3		T15	5
valid_sources[0x13]	2819	1			T1	1		T15	6		T26	3
valid_sources[0x14]	2412	1			T14	5		T15	4		T26	3
valid_sources[0x15]	5459	1			T14	5		T26	4		T55	1
valid_sources[0x16]	2096	1			T9	1		T14	1		T26	2
valid_sources[0x17]	2073	1			T7	1		T9	1		T14	5
valid_sources[0x18]	2203	1			T3	3		T7	3		T14	2
valid_sources[0x19]	2883	1			T14	3		T26	5		T55	1
valid_sources[0x1a]	2519	1			T1	1		T14	6		T26	8
valid_sources[0x1b]	3089	1			T14	2		T26	4		T44	4
valid_sources[0x1c]	1978	1			T9	1		T14	7		T26	1
valid_sources[0x1d]	3466	1			T3	21		T14	5		T15	2
valid_sources[0x1e]	2438	1			T7	1		T9	1		T14	3
valid_sources[0x1f]	3651	1			T14	6		T26	2		T55	1
valid_sources[0x20]	1840	1			T14	3		T26	6		T143	1
valid_sources[0x21]	3599	1			T3	2		T14	3		T15	1
valid_sources[0x22]	1944	1			T1	4		T14	1		T15	2
valid_sources[0x23]	4319	1			T1	1		T7	1		T10	28
valid_sources[0x24]	2221	1			T1	1		T9	1		T14	2
valid_sources[0x25]	3012	1			T1	1		T14	13		T26	6
valid_sources[0x26]	1897	1			T7	3		T9	3		T14	1
valid_sources[0x27]	2860	1			T9	1		T14	2		T15	6
valid_sources[0x28]	2012	1			T3	1		T7	6		T14	5
valid_sources[0x29]	2853	1			T14	4		T26	1		T54	1
valid_sources[0x2a]	2908	1			T14	2		T26	3		T54	4
valid_sources[0x2b]	2592	1			T3	15		T9	1		T14	5
valid_sources[0x2c]	2205	1			T1	2		T14	2		T26	6
valid_sources[0x2d]	4377	1			T7	2		T14	4		T26	3
valid_sources[0x2e]	2246	1			T1	1		T14	2		T26	3
valid_sources[0x2f]	2458	1			T1	2		T9	1		T14	6
valid_sources[0x30]	2512	1			T3	1		T7	1		T9	1
valid_sources[0x31]	2437	1			T3	1		T9	2		T14	3
valid_sources[0x32]	2697	1			T26	1		T143	3		T55	1
valid_sources[0x33]	2013	1			T14	2		T26	6		T143	1
valid_sources[0x34]	2332	1			T7	1		T14	7		T26	2
valid_sources[0x35]	2130	1			T14	2		T15	4		T26	3
valid_sources[0x36]	2111	1			T14	1		T54	1		T55	1
valid_sources[0x37]	2154	1			T14	4		T26	2		T54	2
valid_sources[0x38]	2441	1			T1	2		T10	8		T14	6
valid_sources[0x39]	2213	1			T1	1		T9	1		T14	5
valid_sources[0x3a]	3162	1			T14	2		T55	1		T16	17
valid_sources[0x3b]	1872	1			T1	1		T14	3		T26	5
valid_sources[0x3c]	2364	1			T14	2		T26	4		T12	1
valid_sources[0x3d]	2203	1			T7	2		T14	4		T26	2
valid_sources[0x3e]	4209	1			T14	3		T26	2		T143	3
valid_sources[0x3f]	2312	1			T7	1		T14	3		T26	7
valid_sources[0x40]	2194	1			T14	1		T26	3		T143	1
valid_sources[0x41]	2307	1			T14	6		T15	1		T26	3
valid_sources[0x42]	2957	1			T7	1		T14	1		T26	2
valid_sources[0x43]	2084	1			T1	1		T14	2		T15	2
valid_sources[0x44]	3004	1			T7	2		T14	4		T15	2
valid_sources[0x45]	2444	1			T9	1		T14	2		T26	1
valid_sources[0x46]	2527	1			T7	2		T9	1		T14	4
valid_sources[0x47]	2854	1			T14	3		T15	1		T26	1
valid_sources[0x48]	2958	1			T14	1		T26	1		T54	1
valid_sources[0x49]	2839	1			T1	1		T7	1		T54	1
valid_sources[0x4a]	3835	1			T7	1		T14	5		T26	1
valid_sources[0x4b]	2016	1			T1	1		T15	3		T26	4
valid_sources[0x4c]	1949	1			T1	1		T14	4		T15	8
valid_sources[0x4d]	2407	1			T14	9		T26	3		T54	1
valid_sources[0x4e]	3625	1			T14	6		T26	1		T54	2
valid_sources[0x4f]	2147	1			T1	2		T7	2		T14	6
valid_sources[0x50]	2171	1			T14	5		T15	2		T26	3
valid_sources[0x51]	2209	1			T7	1		T14	4		T15	2
valid_sources[0x52]	2776	1			T14	6		T15	3		T26	1
valid_sources[0x53]	5584	1			T1	2		T3	1		T7	1
valid_sources[0x54]	2117	1			T1	1		T7	4		T14	4
valid_sources[0x55]	2417	1			T1	2		T14	11		T26	2
valid_sources[0x56]	3658	1			T1	1		T7	2		T14	1
valid_sources[0x57]	2885	1			T7	1		T14	3		T15	3
valid_sources[0x58]	2108	1			T7	2		T14	3		T15	4
valid_sources[0x59]	2600	1			T7	1		T14	5		T26	3
valid_sources[0x5a]	3053	1			T7	3		T14	4		T15	2
valid_sources[0x5b]	3142	1			T7	5		T14	4		T26	4
valid_sources[0x5c]	2256	1			T7	1		T14	13		T15	1
valid_sources[0x5d]	2131	1			T1	1		T7	3		T8	21
valid_sources[0x5e]	2116	1			T1	1		T14	1		T26	6
valid_sources[0x5f]	2022	1			T9	1		T14	3		T26	2
valid_sources[0x60]	2297	1			T3	8		T9	2		T10	27
valid_sources[0x61]	3107	1			T14	3		T26	3		T54	2
valid_sources[0x62]	2298	1			T14	1		T15	1		T26	2
valid_sources[0x63]	2242	1			T9	1		T10	12		T14	3
valid_sources[0x64]	1820	1			T14	2		T26	6		T54	1
valid_sources[0x65]	2511	1			T14	6		T26	5		T54	1
valid_sources[0x66]	1945	1			T7	1		T15	1		T26	4
valid_sources[0x67]	2136	1			T1	1		T14	2		T26	3
valid_sources[0x68]	2059	1			T1	1		T9	1		T14	4
valid_sources[0x69]	2076	1			T3	6		T7	2		T14	2
valid_sources[0x6a]	2196	1			T1	1		T7	1		T14	6
valid_sources[0x6b]	3654	1			T1	1		T7	2		T14	2
valid_sources[0x6c]	2164	1			T1	1		T7	1		T9	1
valid_sources[0x6d]	3428	1			T14	2		T26	3		T78	1
valid_sources[0x6e]	4115	1			T14	3		T26	3		T64	3
valid_sources[0x6f]	3169	1			T1	2		T14	2		T15	1
valid_sources[0x70]	2122	1			T1	1		T3	11		T9	1
valid_sources[0x71]	2913	1			T15	1		T26	4		T54	1
valid_sources[0x72]	2482	1			T14	3		T26	6		T54	2
valid_sources[0x73]	2314	1			T3	3		T7	1		T14	2
valid_sources[0x74]	4396	1			T14	1		T15	5		T26	3
valid_sources[0x75]	3136	1			T14	1		T26	7		T143	6
valid_sources[0x76]	2130	1			T7	1		T14	4		T26	7
valid_sources[0x77]	1934	1			T1	1		T26	1		T54	3
valid_sources[0x78]	3142	1			T1	1		T14	2		T26	2
valid_sources[0x79]	3678	1			T9	1		T14	1		T26	4
valid_sources[0x7a]	2571	1			T9	1		T14	3		T26	8
valid_sources[0x7b]	2206	1			T9	1		T14	4		T15	1
valid_sources[0x7c]	1862	1			T1	3		T9	1		T14	2
valid_sources[0x7d]	2947	1			T7	2		T10	1		T14	2
valid_sources[0x7e]	1990	1			T7	1		T9	1		T14	1
valid_sources[0x7f]	2242	1			T1	1		T14	1		T15	1
valid_sources[0x80]	2753	1			T14	13		T26	3		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87933

1

T1

45

T3

15

T5

14

values[0x0]

all_enables

biggest_size

59261

1

T1

3

T3

15

T5

6

values[0x1]

all_enables

biggest_size

31762

1

T1

1

T3

9

T5

1