SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35041 | 1 | T14 | 317 | T26 | 289 | T39 | 311 | ||||
others[1] | 35145 | 1 | T14 | 300 | T26 | 320 | T39 | 285 | ||||
others[2] | 34987 | 1 | T14 | 308 | T26 | 304 | T39 | 297 | ||||
others[3] | 58310 | 1 | T14 | 488 | T26 | 486 | T39 | 502 | ||||
false | 17945 | 1 | T5 | 3 | T14 | 50 | T26 | 50 | ||||
true | 27690 | 1 | T1 | 12 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34900 | 1 | T14 | 286 | T26 | 322 | T39 | 306 | ||||
others[1] | 35070 | 1 | T14 | 317 | T26 | 289 | T39 | 291 | ||||
others[2] | 34772 | 1 | T14 | 281 | T26 | 285 | T39 | 314 | ||||
others[3] | 58620 | 1 | T14 | 517 | T26 | 513 | T39 | 489 | ||||
false | 11551 | 1 | T5 | 4 | T14 | 50 | T26 | 50 | ||||
true | 21381 | 1 | T1 | 12 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 660 | 1 | T1 | 2 | T7 | 1 | T38 | 1 | ||||
others[1] | 644 | 1 | T7 | 1 | T38 | 1 | T143 | 5 | ||||
others[2] | 680 | 1 | T143 | 4 | T40 | 1 | T16 | 9 | ||||
others[3] | 1139 | 1 | T1 | 1 | T10 | 1 | T143 | 7 | ||||
false | 13165 | 1 | T1 | 22 | T2 | 5 | T3 | 1 | ||||
true | 3903 | 1 | T1 | 7 | T5 | 2 | T7 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |