Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22512814	12411	0	0
intr_enable_rd_A	22512814	55088	0	0
reset_en_rd_A	22512814	1609	0	0
reset_en_regwen_rd_A	22512814	1476	0	0
wake_info_capture_dis_rd_A	22512814	1579	0	0
wakeup_en_rd_A	22512814	2585	0	0
wakeup_en_regwen_rd_A	22512814	1555	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	12411	0	0
T16	89081	2	0	0
T17	3062	0	0	0
T24	0	12	0	0
T25	0	15	0	0
T41	2677	0	0	0
T46	0	24	0	0
T71	0	35	0	0
T77	53817	0	0	0
T79	62540	0	0	0
T80	2621	0	0	0
T81	34936	0	0	0
T82	0	11	0	0
T83	0	18	0	0
T90	0	21	0	0
T109	1185	0	0	0
T146	0	4	0	0
T147	0	2	0	0
T148	3212	0	0	0
T149	1317	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	55088	0	0
T12	15679	0	0	0
T15	3357	24	0	0
T16	0	746	0	0
T17	0	62	0	0
T26	37546	0	0	0
T31	0	22	0	0
T34	0	158	0	0
T38	5526	0	0	0
T39	0	149	0	0
T42	1383	0	0	0
T44	1879	0	0	0
T54	6577	0	0	0
T55	16656	0	0	0
T60	0	52	0	0
T64	1224	0	0	0
T76	0	3	0	0
T79	0	193	0	0
T109	0	3	0	0
T143	4793	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	1609	0	0
T46	411938	2	0	0
T82	0	11	0	0
T85	0	6	0	0
T88	7194	0	0	0
T89	3534	0	0	0
T90	167331	0	0	0
T91	7999	0	0	0
T92	15095	0	0	0
T93	35820	0	0	0
T94	17103	0	0	0
T95	2051	0	0	0
T96	1108	0	0	0
T97	0	9	0	0
T146	0	7	0	0
T147	0	4	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	7	0	0
T153	0	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	1476	0	0
T46	411938	9	0	0
T82	0	4	0	0
T85	0	6	0	0
T87	0	7	0	0
T88	7194	0	0	0
T89	3534	0	0	0
T90	167331	0	0	0
T91	7999	0	0	0
T92	15095	0	0	0
T93	35820	0	0	0
T94	17103	0	0	0
T95	2051	0	0	0
T96	1108	0	0	0
T97	0	15	0	0
T146	0	4	0	0
T147	0	10	0	0
T150	0	11	0	0
T151	0	12	0	0
T154	0	4	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	1579	0	0
T46	411938	4	0	0
T82	0	9	0	0
T85	0	8	0	0
T87	0	1	0	0
T88	7194	0	0	0
T89	3534	0	0	0
T90	167331	0	0	0
T91	7999	0	0	0
T92	15095	0	0	0
T93	35820	0	0	0
T94	17103	0	0	0
T95	2051	0	0	0
T96	1108	0	0	0
T97	0	16	0	0
T146	0	4	0	0
T147	0	7	0	0
T150	0	15	0	0
T151	0	8	0	0
T155	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	2585	0	0
T46	411938	6	0	0
T82	0	9	0	0
T87	0	9	0	0
T88	7194	0	0	0
T89	3534	0	0	0
T90	167331	0	0	0
T91	7999	0	0	0
T92	15095	0	0	0
T93	35820	0	0	0
T94	17103	0	0	0
T95	2051	0	0	0
T96	1108	0	0	0
T97	0	29	0	0
T146	0	6	0	0
T147	0	12	0	0
T150	0	8	0	0
T151	0	10	0	0
T152	0	12	0	0
T155	0	7	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22512814	1555	0	0
T46	411938	7	0	0
T82	0	9	0	0
T87	0	5	0	0
T88	7194	0	0	0
T89	3534	0	0	0
T90	167331	0	0	0
T91	7999	0	0	0
T92	15095	0	0	0
T93	35820	0	0	0
T94	17103	0	0	0
T95	2051	0	0	0
T96	1108	0	0	0
T97	0	15	0	0
T146	0	7	0	0
T147	0	13	0	0
T150	0	8	0	0
T151	0	1	0	0
T152	0	11	0	0
T155	0	1	0	0