Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	65778105	138218	0	0
StatusRise_A	65778105	154426	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65778105	138218	0	0
T1	9606	54	0	0
T2	8814	0	0	0
T3	5667	23	0	0
T4	1917	0	0	0
T5	15870	18	0	0
T6	9042	12	0	0
T7	9033	54	0	0
T8	6882	12	0	0
T9	6816	6	0	0
T10	8817	54	0	0
T11	0	3	0	0
T14	0	192	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65778105	154426	0	0
T1	9606	57	0	0
T2	8814	15	0	0
T3	5667	25	0	0
T4	1917	9	0	0
T5	15870	24	0	0
T6	9042	15	0	0
T7	9033	60	0	0
T8	6882	15	0	0
T9	6816	9	0	0
T10	8817	60	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21926035	51195	0	0
StatusRise_A	21926035	57049	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	51195	0	0
T1	3202	18	0	0
T2	2938	0	0	0
T3	1889	9	0	0
T4	639	0	0	0
T5	5290	6	0	0
T6	3014	4	0	0
T7	3011	18	0	0
T8	2294	4	0	0
T9	2272	2	0	0
T10	2939	18	0	0
T11	0	1	0	0
T14	0	77	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	57049	0	0
T1	3202	19	0	0
T2	2938	5	0	0
T3	1889	10	0	0
T4	639	3	0	0
T5	5290	8	0	0
T6	3014	5	0	0
T7	3011	20	0	0
T8	2294	5	0	0
T9	2272	3	0	0
T10	2939	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21926035	51195	0	0
StatusRise_A	21926035	57050	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	51195	0	0
T1	3202	18	0	0
T2	2938	0	0	0
T3	1889	9	0	0
T4	639	0	0	0
T5	5290	6	0	0
T6	3014	4	0	0
T7	3011	18	0	0
T8	2294	4	0	0
T9	2272	2	0	0
T10	2939	18	0	0
T11	0	1	0	0
T14	0	77	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	57050	0	0
T1	3202	19	0	0
T2	2938	5	0	0
T3	1889	10	0	0
T4	639	3	0	0
T5	5290	8	0	0
T6	3014	5	0	0
T7	3011	20	0	0
T8	2294	5	0	0
T9	2272	3	0	0
T10	2939	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	21926035	35828	0	0
StatusRise_A	21926035	40327	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	35828	0	0
T1	3202	18	0	0
T2	2938	0	0	0
T3	1889	5	0	0
T4	639	0	0	0
T5	5290	6	0	0
T6	3014	4	0	0
T7	3011	18	0	0
T8	2294	4	0	0
T9	2272	2	0	0
T10	2939	18	0	0
T11	0	1	0	0
T14	0	38	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	40327	0	0
T1	3202	19	0	0
T2	2938	5	0	0
T3	1889	5	0	0
T4	639	3	0	0
T5	5290	8	0	0
T6	3014	5	0	0
T7	3011	20	0	0
T8	2294	5	0	0
T9	2272	3	0	0
T10	2939	20	0	0