Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	21926622	5619	0	0
EscTimeoutStoppedByClReset_A	21926035	2939028	0	0
EscTimeoutTriggersReset_A	5112193	345	0	0
RomAllowActiveState_A	21926035	56656	0	0
RomAllowCheckGoodState_A	21926035	56710	0	0
RomBlockActiveState_A	21926035	30474	0	0
RomBlockCheckGoodState_A	21926035	410882	0	0
RomIntgChkDisFalse_A	21926035	21294899	0	0
RomIntgChkDisTrue_A	21926035	127331	0	0
RstreqChkEsctimeout_A	21926035	4215	0	0
RstreqChkFsmterm_A	21926035	140	0	0
RstreqChkGlbesc_A	21926035	4215	0	0
RstreqChkMainpd_A	21926035	898770	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926622	5619	0	0
T11	15372	110	0	0
T12	15680	216	0	0
T13	0	32	0	0
T15	3358	0	0	0
T26	37546	0	0	0
T30	0	56	0	0
T38	5527	0	0	0
T44	1879	0	0	0
T54	6578	0	0	0
T55	16656	0	0	0
T64	1225	0	0	0
T92	0	52	0	0
T106	0	56	0	0
T107	0	55	0	0
T143	4793	0	0	0
T156	0	11	0	0
T157	0	7	0	0
T158	0	2	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	2939028	0	0
T1	3202	421	0	0
T2	2938	35	0	0
T3	1889	314	0	0
T4	639	9	0	0
T5	5290	249	0	0
T6	3014	65	0	0
T7	3011	355	0	0
T8	2294	147	0	0
T9	2272	25	0	0
T10	2939	361	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5112193	345	0	0
T11	372	3	0	0
T12	200	3	0	0
T13	0	2	0	0
T15	265	0	0	0
T26	6359	0	0	0
T30	0	3	0	0
T38	625	0	0	0
T44	351	0	0	0
T54	1465	0	0	0
T55	1947	0	0	0
T64	358	0	0	0
T92	0	2	0	0
T106	0	3	0	0
T107	0	3	0	0
T143	593	0	0	0
T156	0	4	0	0
T157	0	5	0	0
T158	0	10	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	56656	0	0
T1	3202	12	0	0
T2	2938	5	0	0
T3	1889	10	0	0
T4	639	3	0	0
T5	5290	8	0	0
T6	3014	5	0	0
T7	3011	13	0	0
T8	2294	5	0	0
T9	2272	3	0	0
T10	2939	13	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	56710	0	0
T1	3202	13	0	0
T2	2938	5	0	0
T3	1889	10	0	0
T4	639	3	0	0
T5	5290	8	0	0
T6	3014	5	0	0
T7	3011	14	0	0
T8	2294	5	0	0
T9	2272	3	0	0
T10	2939	14	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	30474	0	0
T5	5290	1072	0	0
T6	3014	0	0	0
T7	3011	0	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	0	0	0
T11	15372	0	0	0
T14	20795	0	0	0
T15	3357	0	0	0
T26	37546	0	0	0
T33	0	248	0	0
T45	0	23	0	0
T159	0	13	0	0
T160	0	13	0	0
T161	0	533	0	0
T162	0	617	0	0
T163	0	200	0	0
T164	0	292	0	0
T165	0	6	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	410882	0	0
T5	5290	871	0	0
T6	3014	0	0	0
T7	3011	0	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	0	0	0
T11	15372	0	0	0
T14	20795	1350	0	0
T15	3357	0	0	0
T16	0	1011	0	0
T24	0	1101	0	0
T26	37546	2626	0	0
T39	0	1311	0	0
T77	0	4060	0	0
T79	0	4114	0	0
T81	0	2309	0	0
T148	0	23	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	21294899	0	0
T1	3202	2402	0	0
T2	2938	2585	0	0
T3	1889	1810	0	0
T4	639	415	0	0
T5	5290	5048	0	0
T6	3014	2671	0	0
T7	3011	1980	0	0
T8	2294	1978	0	0
T9	2272	2200	0	0
T10	2939	1987	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	127331	0	0
T5	5290	94	0	0
T6	3014	0	0	0
T7	3011	0	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	0	0	0
T11	15372	0	0	0
T14	20795	263	0	0
T15	3357	0	0	0
T26	37546	344	0	0
T33	0	920	0	0
T39	0	191	0	0
T45	0	370	0	0
T166	0	1966	0	0
T167	0	2067	0	0
T168	0	205	0	0
T169	0	24752	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	4215	0	0
T1	3202	4	0	0
T2	2938	4	0	0
T3	1889	0	0	0
T4	639	0	0	0
T5	5290	2	0	0
T6	3014	0	0	0
T7	3011	5	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	7	0	0
T11	0	1	0	0
T12	0	1	0	0
T38	0	6	0	0
T40	0	7	0	0
T42	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	140	0	0
T21	44970	40	0	0
T22	0	20	0	0
T23	0	20	0	0
T27	0	20	0	0
T28	0	40	0	0
T29	4450	0	0	0
T30	14921	0	0	0
T31	7221	0	0	0
T32	3133	0	0	0
T33	1778	0	0	0
T34	25572	0	0	0
T35	1513	0	0	0
T36	4882	0	0	0
T37	1456	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	4215	0	0
T1	3202	4	0	0
T2	2938	4	0	0
T3	1889	0	0	0
T4	639	0	0	0
T5	5290	2	0	0
T6	3014	0	0	0
T7	3011	5	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	7	0	0
T11	0	1	0	0
T12	0	1	0	0
T38	0	6	0	0
T40	0	7	0	0
T42	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21926035	898770	0	0
T1	3202	90	0	0
T2	2938	0	0	0
T3	1889	0	0	0
T4	639	6	0	0
T5	5290	439	0	0
T6	3014	0	0	0
T7	3011	187	0	0
T8	2294	0	0	0
T9	2272	0	0	0
T10	2939	152	0	0
T14	0	1293	0	0
T26	0	2754	0	0
T38	0	209	0	0
T39	0	1753	0	0
T64	0	25	0	0