Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	506526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

196228

1

T1

11

T2

209

T4

1426

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	373470	1			T1	19		T2	427		T3	1
values[0x0]	164550	1			T1	6		T2	201		T4	1567
values[0x1]	164734	1			T1	10		T2	251		T4	1525

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	401116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

301638

1

T1

14

T2

352

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2915	1			T4	15		T14	37		T33	3
valid_sources[0x01]	2850	1			T2	6		T4	22		T14	29
valid_sources[0x02]	2504	1			T2	3		T4	22		T21	1
valid_sources[0x03]	2329	1			T2	14		T4	25		T14	45
valid_sources[0x04]	2386	1			T2	5		T4	15		T21	1
valid_sources[0x05]	2673	1			T4	23		T37	1		T14	48
valid_sources[0x06]	2547	1			T2	5		T4	21		T9	1
valid_sources[0x07]	2266	1			T2	3		T4	24		T14	40
valid_sources[0x08]	2455	1			T2	1		T4	8		T21	1
valid_sources[0x09]	2688	1			T4	22		T14	44		T22	14
valid_sources[0x0a]	2254	1			T4	12		T14	37		T35	1
valid_sources[0x0b]	2301	1			T2	1		T4	21		T9	2
valid_sources[0x0c]	2938	1			T2	6		T4	15		T6	1
valid_sources[0x0d]	3289	1			T4	11		T9	2		T14	47
valid_sources[0x0e]	2758	1			T2	3		T4	39		T9	1
valid_sources[0x0f]	2406	1			T2	2		T4	27		T9	1
valid_sources[0x10]	2287	1			T4	10		T14	39		T33	7
valid_sources[0x11]	2286	1			T2	5		T4	17		T41	2
valid_sources[0x12]	2574	1			T2	11		T4	32		T37	1
valid_sources[0x13]	3408	1			T2	2		T4	33		T37	1
valid_sources[0x14]	2417	1			T2	3		T4	18		T14	50
valid_sources[0x15]	3737	1			T4	23		T6	1		T14	53
valid_sources[0x16]	3405	1			T2	3		T4	19		T14	37
valid_sources[0x17]	2800	1			T2	3		T4	28		T6	1
valid_sources[0x18]	2067	1			T4	11		T14	30		T62	1
valid_sources[0x19]	6418	1			T2	3		T4	20		T9	1
valid_sources[0x1a]	2371	1			T2	3		T4	30		T21	1
valid_sources[0x1b]	2402	1			T4	10		T6	2		T9	1
valid_sources[0x1c]	2337	1			T2	16		T4	29		T10	3
valid_sources[0x1d]	2415	1			T2	6		T4	22		T6	2
valid_sources[0x1e]	2392	1			T2	1		T4	17		T37	1
valid_sources[0x1f]	2530	1			T2	1		T4	28		T14	50
valid_sources[0x20]	2465	1			T2	3		T4	25		T14	48
valid_sources[0x21]	2534	1			T2	4		T4	28		T6	1
valid_sources[0x22]	2209	1			T2	1		T4	33		T37	1
valid_sources[0x23]	2351	1			T2	4		T4	29		T14	39
valid_sources[0x24]	2720	1			T2	2		T4	18		T21	1
valid_sources[0x25]	2500	1			T4	32		T6	1		T21	4
valid_sources[0x26]	2337	1			T4	15		T9	1		T21	1
valid_sources[0x27]	2362	1			T4	50		T14	48		T22	4
valid_sources[0x28]	2585	1			T4	18		T9	2		T14	48
valid_sources[0x29]	3404	1			T2	3		T4	12		T9	1
valid_sources[0x2a]	12170	1			T2	7		T4	21		T14	43
valid_sources[0x2b]	2681	1			T4	35		T6	2		T21	1
valid_sources[0x2c]	2627	1			T2	3		T4	23		T14	37
valid_sources[0x2d]	3492	1			T2	12		T4	15		T6	1
valid_sources[0x2e]	2656	1			T2	4		T4	30		T9	1
valid_sources[0x2f]	2330	1			T2	1		T4	27		T14	41
valid_sources[0x30]	3864	1			T4	24		T6	1		T37	1
valid_sources[0x31]	2986	1			T2	3		T4	15		T14	52
valid_sources[0x32]	2556	1			T2	10		T4	22		T7	1
valid_sources[0x33]	2516	1			T2	2		T4	26		T14	34
valid_sources[0x34]	2451	1			T4	14		T6	1		T10	4
valid_sources[0x35]	2239	1			T2	3		T4	25		T6	1
valid_sources[0x36]	2215	1			T2	1		T4	21		T14	42
valid_sources[0x37]	2503	1			T2	4		T4	36		T14	30
valid_sources[0x38]	2562	1			T1	13		T2	2		T4	21
valid_sources[0x39]	2559	1			T2	6		T4	14		T6	3
valid_sources[0x3a]	2209	1			T2	3		T4	12		T14	30
valid_sources[0x3b]	2393	1			T2	2		T4	18		T9	1
valid_sources[0x3c]	3228	1			T2	4		T4	21		T9	1
valid_sources[0x3d]	2243	1			T4	4		T9	1		T21	1
valid_sources[0x3e]	2481	1			T2	4		T4	25		T21	1
valid_sources[0x3f]	2312	1			T2	4		T4	19		T21	1
valid_sources[0x40]	4023	1			T2	1		T4	43		T6	2
valid_sources[0x41]	2451	1			T2	2		T4	18		T14	42
valid_sources[0x42]	2255	1			T4	36		T14	43		T22	8
valid_sources[0x43]	2767	1			T2	1		T4	22		T6	1
valid_sources[0x44]	4378	1			T4	25		T14	37		T22	15
valid_sources[0x45]	4245	1			T2	6		T4	23		T6	3
valid_sources[0x46]	2856	1			T4	23		T14	50		T22	11
valid_sources[0x47]	2281	1			T2	2		T4	22		T21	1
valid_sources[0x48]	2635	1			T2	9		T4	28		T41	8
valid_sources[0x49]	2254	1			T4	39		T14	49		T33	4
valid_sources[0x4a]	2436	1			T4	18		T21	1		T14	31
valid_sources[0x4b]	3466	1			T4	19		T6	2		T14	41
valid_sources[0x4c]	2412	1			T2	2		T4	22		T14	26
valid_sources[0x4d]	2467	1			T4	15		T9	1		T14	33
valid_sources[0x4e]	2240	1			T2	1		T4	29		T14	45
valid_sources[0x4f]	2270	1			T2	6		T4	29		T21	2
valid_sources[0x50]	2351	1			T2	5		T4	32		T6	2
valid_sources[0x51]	2353	1			T4	26		T6	2		T41	9
valid_sources[0x52]	2535	1			T2	4		T4	23		T37	1
valid_sources[0x53]	3248	1			T2	7		T4	14		T14	45
valid_sources[0x54]	2815	1			T2	6		T4	18		T21	3
valid_sources[0x55]	2843	1			T2	1		T4	21		T9	1
valid_sources[0x56]	2459	1			T4	44		T9	1		T14	40
valid_sources[0x57]	2741	1			T2	2		T4	11		T14	49
valid_sources[0x58]	3232	1			T2	6		T4	23		T5	1
valid_sources[0x59]	2388	1			T2	3		T4	28		T6	1
valid_sources[0x5a]	2376	1			T2	9		T4	16		T6	1
valid_sources[0x5b]	3150	1			T2	8		T4	27		T6	1
valid_sources[0x5c]	2368	1			T4	21		T14	45		T33	2
valid_sources[0x5d]	2289	1			T2	5		T4	23		T10	3
valid_sources[0x5e]	2353	1			T4	20		T9	1		T14	50
valid_sources[0x5f]	2518	1			T2	12		T4	33		T9	2
valid_sources[0x60]	2238	1			T4	18		T14	44		T22	3
valid_sources[0x61]	4305	1			T2	4		T4	15		T14	51
valid_sources[0x62]	2463	1			T4	22		T37	1		T21	3
valid_sources[0x63]	2463	1			T4	18		T9	1		T14	36
valid_sources[0x64]	2304	1			T1	16		T2	5		T4	11
valid_sources[0x65]	3784	1			T2	1		T4	19		T14	43
valid_sources[0x66]	2649	1			T2	4		T4	32		T14	45
valid_sources[0x67]	3226	1			T2	5		T4	32		T14	50
valid_sources[0x68]	3565	1			T2	4		T4	22		T9	1
valid_sources[0x69]	3001	1			T2	5		T4	28		T14	27
valid_sources[0x6a]	2563	1			T2	8		T4	23		T14	62
valid_sources[0x6b]	2631	1			T2	6		T4	17		T9	1
valid_sources[0x6c]	2332	1			T2	7		T4	11		T14	29
valid_sources[0x6d]	2280	1			T2	15		T4	20		T14	42
valid_sources[0x6e]	2349	1			T2	8		T4	20		T14	40
valid_sources[0x6f]	2776	1			T2	6		T4	36		T37	1
valid_sources[0x70]	2362	1			T2	5		T4	12		T14	37
valid_sources[0x71]	2377	1			T2	5		T4	17		T9	2
valid_sources[0x72]	3696	1			T2	5		T4	19		T9	1
valid_sources[0x73]	2265	1			T2	4		T4	36		T10	12
valid_sources[0x74]	2534	1			T4	15		T9	2		T37	2
valid_sources[0x75]	2607	1			T2	8		T4	4		T14	45
valid_sources[0x76]	2508	1			T4	24		T6	2		T9	1
valid_sources[0x77]	3290	1			T2	4		T4	21		T37	1
valid_sources[0x78]	2437	1			T2	1		T4	19		T9	1
valid_sources[0x79]	3398	1			T4	16		T14	44		T34	1
valid_sources[0x7a]	2569	1			T2	4		T4	6		T6	1
valid_sources[0x7b]	2446	1			T4	12		T6	1		T14	49
valid_sources[0x7c]	2286	1			T2	5		T4	18		T14	33
valid_sources[0x7d]	2200	1			T2	1		T4	16		T9	2
valid_sources[0x7e]	2796	1			T2	1		T4	18		T21	1
valid_sources[0x7f]	2615	1			T4	16		T6	1		T14	38
valid_sources[0x80]	2585	1			T4	10		T6	2		T37	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

101527

1

T1

7

T2

88

T4

568

values[0x0]

all_enables

biggest_size

61241

1

T1

2

T2

71

T4

578

values[0x1]

all_enables

biggest_size

33460

1

T1

2

T2

50

T4

280