SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35048 | 1 | T2 | 395 | T4 | 1 | T22 | 291 | ||||
others[1] | 35005 | 1 | T2 | 434 | T22 | 297 | T39 | 1 | ||||
others[2] | 35034 | 1 | T2 | 386 | T4 | 1 | T9 | 1 | ||||
others[3] | 58339 | 1 | T2 | 668 | T9 | 2 | T22 | 530 | ||||
false | 18929 | 1 | T2 | 50 | T4 | 169 | T9 | 2 | ||||
true | 28912 | 1 | T1 | 1 | T2 | 102 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34899 | 1 | T2 | 428 | T4 | 1 | T22 | 290 | ||||
others[1] | 34955 | 1 | T2 | 377 | T4 | 1 | T22 | 303 | ||||
others[2] | 35058 | 1 | T2 | 373 | T4 | 1 | T22 | 319 | ||||
others[3] | 58455 | 1 | T2 | 670 | T22 | 492 | T39 | 1 | ||||
false | 12060 | 1 | T2 | 50 | T4 | 86 | T9 | 3 | ||||
true | 22097 | 1 | T1 | 1 | T2 | 102 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 714 | 1 | T4 | 4 | T9 | 1 | T14 | 5 | ||||
others[1] | 721 | 1 | T4 | 2 | T14 | 12 | T20 | 7 | ||||
others[2] | 723 | 1 | T4 | 3 | T6 | 1 | T9 | 1 | ||||
others[3] | 1162 | 1 | T4 | 3 | T6 | 1 | T21 | 1 | ||||
false | 13831 | 1 | T1 | 1 | T2 | 2 | T3 | 6 | ||||
true | 4167 | 1 | T4 | 33 | T6 | 6 | T9 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |