Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24506396	16014	0	0
intr_enable_rd_A	24506396	39776	0	0
reset_en_rd_A	24506396	1675	0	0
reset_en_regwen_rd_A	24506396	1438	0	0
wake_info_capture_dis_rd_A	24506396	1519	0	0
wakeup_en_rd_A	24506396	2090	0	0
wakeup_en_regwen_rd_A	24506396	1471	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	16014	0	0
T4	148985	3	0	0
T5	1365	0	0	0
T6	2087	0	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	0	0	0
T10	6404	0	0	0
T14	0	42	0	0
T20	0	12	0	0
T21	1703	0	0	0
T37	1515	0	0	0
T41	3032	0	0	0
T48	0	50	0	0
T49	0	110	0	0
T83	0	10	0	0
T84	0	3	0	0
T91	0	2	0	0
T103	0	47	0	0
T138	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	39776	0	0
T9	1850	8	0	0
T10	6404	0	0	0
T14	294267	0	0	0
T21	1703	0	0	0
T22	17123	0	0	0
T33	10104	0	0	0
T37	1515	0	0	0
T38	2886	0	0	0
T39	0	24	0	0
T40	0	20	0	0
T41	3032	0	0	0
T62	7763	0	0	0
T80	0	493	0	0
T81	0	31	0	0
T82	0	9	0	0
T98	0	92	0	0
T106	0	16	0	0
T139	0	48	0	0
T140	0	36	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	1675	0	0
T49	821015	0	0	0
T72	0	3	0	0
T73	0	10	0	0
T84	159215	2	0	0
T88	0	15	0	0
T93	0	7	0	0
T110	1444	0	0	0
T141	0	21	0	0
T142	0	8	0	0
T143	0	8	0	0
T144	0	20	0	0
T145	0	9	0	0
T146	17514	0	0	0
T147	2326	0	0	0
T148	3567	0	0	0
T149	21293	0	0	0
T150	3545	0	0	0
T151	1325	0	0	0
T152	1221	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	1438	0	0
T45	0	1	0	0
T49	821015	0	0	0
T73	0	7	0	0
T84	159215	9	0	0
T88	0	11	0	0
T93	0	12	0	0
T110	1444	0	0	0
T141	0	19	0	0
T144	0	13	0	0
T145	0	9	0	0
T146	17514	0	0	0
T147	2326	0	0	0
T148	3567	0	0	0
T149	21293	0	0	0
T150	3545	0	0	0
T151	1325	0	0	0
T152	1221	0	0	0
T153	0	1	0	0
T154	0	6	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	1519	0	0
T49	821015	0	0	0
T72	0	1	0	0
T73	0	6	0	0
T84	159215	5	0	0
T88	0	6	0	0
T93	0	15	0	0
T110	1444	0	0	0
T141	0	21	0	0
T143	0	7	0	0
T144	0	15	0	0
T145	0	15	0	0
T146	17514	0	0	0
T147	2326	0	0	0
T148	3567	0	0	0
T149	21293	0	0	0
T150	3545	0	0	0
T151	1325	0	0	0
T152	1221	0	0	0
T153	0	8	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	2090	0	0
T49	821015	0	0	0
T72	0	6	0	0
T84	159215	12	0	0
T88	0	10	0	0
T93	0	8	0	0
T110	1444	0	0	0
T141	0	12	0	0
T143	0	14	0	0
T144	0	7	0	0
T145	0	14	0	0
T146	17514	0	0	0
T147	2326	0	0	0
T148	3567	0	0	0
T149	21293	0	0	0
T150	3545	0	0	0
T151	1325	0	0	0
T152	1221	0	0	0
T153	0	2	0	0
T154	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506396	1471	0	0
T49	821015	0	0	0
T73	0	9	0	0
T84	159215	10	0	0
T88	0	8	0	0
T93	0	18	0	0
T110	1444	0	0	0
T141	0	10	0	0
T142	0	6	0	0
T143	0	13	0	0
T144	0	11	0	0
T145	0	15	0	0
T146	17514	0	0	0
T147	2326	0	0	0
T148	3567	0	0	0
T149	21293	0	0	0
T150	3545	0	0	0
T151	1325	0	0	0
T152	1221	0	0	0
T153	0	4	0	0