Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71873118	142650	0	0
StatusRise_A	71873118	159386	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71873118	142650	0	0
T1	2289	6	0	0
T2	177054	236	0	0
T3	5937	0	0	0
T4	446955	1301	0	0
T5	4095	0	0	0
T6	6261	54	0	0
T7	5151	0	0	0
T8	5427	0	0	0
T9	5550	15	0	0
T10	19212	27	0	0
T14	0	2167	0	0
T21	0	15	0	0
T37	0	12	0	0
T41	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71873118	159386	0	0
T1	2289	9	0	0
T2	177054	241	0	0
T3	5937	18	0	0
T4	446955	1447	0	0
T5	4095	15	0	0
T6	6261	60	0	0
T7	5151	18	0	0
T8	5427	6	0	0
T9	5550	21	0	0
T10	19212	30	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23957706	52887	0	0
StatusRise_A	23957706	58935	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	52887	0	0
T1	763	2	0	0
T2	59018	89	0	0
T3	1979	0	0	0
T4	148985	480	0	0
T5	1365	0	0	0
T6	2087	18	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	5	0	0
T10	6404	10	0	0
T14	0	791	0	0
T21	0	5	0	0
T37	0	4	0	0
T41	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	58935	0	0
T1	763	3	0	0
T2	59018	91	0	0
T3	1979	6	0	0
T4	148985	533	0	0
T5	1365	5	0	0
T6	2087	20	0	0
T7	1717	6	0	0
T8	1809	2	0	0
T9	1850	7	0	0
T10	6404	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23957706	52887	0	0
StatusRise_A	23957706	58935	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	52887	0	0
T1	763	2	0	0
T2	59018	89	0	0
T3	1979	0	0	0
T4	148985	480	0	0
T5	1365	0	0	0
T6	2087	18	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	5	0	0
T10	6404	10	0	0
T14	0	791	0	0
T21	0	5	0	0
T37	0	4	0	0
T41	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	58935	0	0
T1	763	3	0	0
T2	59018	91	0	0
T3	1979	6	0	0
T4	148985	533	0	0
T5	1365	5	0	0
T6	2087	20	0	0
T7	1717	6	0	0
T8	1809	2	0	0
T9	1850	7	0	0
T10	6404	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23957706	36876	0	0
StatusRise_A	23957706	41516	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	36876	0	0
T1	763	2	0	0
T2	59018	58	0	0
T3	1979	0	0	0
T4	148985	341	0	0
T5	1365	0	0	0
T6	2087	18	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	5	0	0
T10	6404	7	0	0
T14	0	585	0	0
T21	0	5	0	0
T37	0	4	0	0
T41	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	41516	0	0
T1	763	3	0	0
T2	59018	59	0	0
T3	1979	6	0	0
T4	148985	381	0	0
T5	1365	5	0	0
T6	2087	20	0	0
T7	1717	6	0	0
T8	1809	2	0	0
T9	1850	7	0	0
T10	6404	8	0	0